Prep for merging 3.4: Undo changes from 3.3 branch

lib/Target/PowerPC/PPCInstrInfo.cpp

 //===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains the PowerPC implementation of the TargetInstrInfo class.
@@ skipping 1078 matching lines @@
 
 bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
                                         unsigned SrcReg, unsigned SrcReg2,
                                         int Mask, int Value,
                                         const MachineRegisterInfo *MRI) const {
   if (DisableCmpOpt)
     return false;
 
   int OpC = CmpInstr->getOpcode();
   unsigned CRReg = CmpInstr->getOperand(0).getReg();
-
-  // FP record forms set CR1 based on the execption status bits, not a
-  // comparison with zero.
-  if (OpC == PPC::FCMPUS || OpC == PPC::FCMPUD)
-    return false;
+  bool isFP = OpC == PPC::FCMPUS || OpC == PPC::FCMPUD;
+  unsigned CRRecReg = isFP ? PPC::CR1 : PPC::CR0;
 
   // The record forms set the condition register based on a signed comparison
   // with zero (so says the ISA manual). This is not as straightforward as it
   // seems, however, because this is always a 64-bit comparison on PPC64, even
   // for instructions that are 32-bit in nature (like slw for example).
   // So, on PPC32, for unsigned comparisons, we can use the record forms only
   // for equality checks (as those don't depend on the sign). On PPC64,
   // we are restricted to equality for unsigned 64-bit comparisons and for
   // signed 32-bit comparisons the applicability is more restricted.
   bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
@@ skipping 22 matching lines @@
     } else if (is32BitUnsignedCompare) {
       // We can perform this optimization, equality only, if MI is
       // zero-extending.
       if (MIOpC == PPC::CNTLZW || MIOpC == PPC::CNTLZWo ||
           MIOpC == PPC::SLW    || MIOpC == PPC::SLWo ||
           MIOpC == PPC::SRW    || MIOpC == PPC::SRWo) {
         noSub = true;
         equalityOnly = true;
       } else
         return false;
-    } else
+    } else if (!isFP)
       equalityOnly = is64BitUnsignedCompare;
-  } else
+  } else if (!isFP)
     equalityOnly = is32BitUnsignedCompare;
 
   if (equalityOnly) {
     // We need to check the uses of the condition register in order to reject
     // non-equality comparisons.
     for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg),
          IE = MRI->use_end(); I != IE; ++I) {
       MachineInstr *UseMI = &*I;
       if (UseMI->getOpcode() == PPC::BCC) {
         unsigned Pred = UseMI->getOperand(0).getImm();
@@ skipping 52 matching lines @@
   }
 
   // Search for Sub.
   const TargetRegisterInfo *TRI = &getRegisterInfo();
   --I;
   for (; I != E && !noSub; --I) {
     const MachineInstr &Instr = *I;
     unsigned IOpC = Instr.getOpcode();
 
     if (&*I != CmpInstr && (
-        Instr.modifiesRegister(PPC::CR0, TRI) ||
-        Instr.readsRegister(PPC::CR0, TRI)))
+        Instr.modifiesRegister(CRRecReg, TRI) ||
+        Instr.readsRegister(CRRecReg, TRI)))
       // This instruction modifies or uses the record condition register after
       // the one we want to change. While we could do this transformation, it
       // would likely not be profitable. This transformation removes one
       // instruction, and so even forcing RA to generate one move probably
       // makes it unprofitable.
       return false;
 
     // Check whether CmpInstr can be made redundant by the current instruction.
     if ((OpC == PPC::CMPW || OpC == PPC::CMPLW ||
          OpC == PPC::CMPD || OpC == PPC::CMPLD) &&
         (IOpC == PPC::SUBF || IOpC == PPC::SUBF8) &&
         ((Instr.getOperand(1).getReg() == SrcReg &&
           Instr.getOperand(2).getReg() == SrcReg2) ||
         (Instr.getOperand(1).getReg() == SrcReg2 &&
          Instr.getOperand(2).getReg() == SrcReg))) {
       Sub = &*I;
       break;
     }
 
+    if (isFP && (IOpC == PPC::FSUB || IOpC == PPC::FSUBS) &&
+        ((Instr.getOperand(1).getReg() == SrcReg &&
+          Instr.getOperand(2).getReg() == SrcReg2) ||
+        (Instr.getOperand(1).getReg() == SrcReg2 &&
+         Instr.getOperand(2).getReg() == SrcReg))) {
+      Sub = &*I;
+      break;
+    }
+
     if (I == B)
       // The 'and' is below the comparison instruction.
       return false;
   }
 
   // Return false if no candidates exist.
   if (!MI && !Sub)
     return false;
 
   // The single candidate is called MI.
@@ skipping 25 matching lines @@
   // needs to be updated to be based on SUB.  Push the condition code
   // operands to OperandsToUpdate.  If it is safe to remove CmpInstr, the
   // condition code of these operands will be modified.
   bool ShouldSwap = false;
   if (Sub) {
     ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
       Sub->getOperand(2).getReg() == SrcReg;
 
     // The operands to subf are the opposite of sub, so only in the fixed-point
     // case, invert the order.
-    ShouldSwap = !ShouldSwap;
+    if (!isFP)
+      ShouldSwap = !ShouldSwap;
   }
 
   if (ShouldSwap)
     for (MachineRegisterInfo::use_iterator I = MRI->use_begin(CRReg),
          IE = MRI->use_end(); I != IE; ++I) {
       MachineInstr *UseMI = &*I;
       if (UseMI->getOpcode() == PPC::BCC) {
         PPC::Predicate Pred = (PPC::Predicate) UseMI->getOperand(0).getImm();
         assert((!equalityOnly ||
                 Pred == PPC::PRED_EQ || Pred == PPC::PRED_NE) &&
@@ skipping 18 matching lines @@
     }
 
   // Create a new virtual register to hold the value of the CR set by the
   // record-form instruction. If the instruction was not previously in
   // record form, then set the kill flag on the CR.
   CmpInstr->eraseFromParent();
 
   MachineBasicBlock::iterator MII = MI;
   BuildMI(*MI->getParent(), llvm::next(MII), MI->getDebugLoc(),
           get(TargetOpcode::COPY), CRReg)
-    .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
+    .addReg(CRRecReg, MIOpC != NewOpC ? RegState::Kill : 0);
 
   if (MIOpC != NewOpC) {
     // We need to be careful here: we're replacing one instruction with
     // another, and we need to make sure that we get all of the right
     // implicit uses and defs. On the other hand, the caller may be holding
     // an iterator to this instruction, and so we can't delete it (this is
     // specifically the case if this is the instruction directly after the
     // compare).
 
     const MCInstrDesc &NewDesc = get(NewOpC);
@@ skipping 189 matching lines @@
   };
 }
 
 INITIALIZE_PASS(PPCEarlyReturn, DEBUG_TYPE,
                 "PowerPC Early-Return Creation", false, false)
 
 char PPCEarlyReturn::ID = 0;
 FunctionPass*
 llvm::createPPCEarlyReturnPass() { return new PPCEarlyReturn(); }