| Index: src/ia32/lithium-codegen-ia32.cc
|
| diff --git a/src/ia32/lithium-codegen-ia32.cc b/src/ia32/lithium-codegen-ia32.cc
|
| index be7dc44f48019dc1fd942dcae1409cff7ba0d999..ecf9bea9efe4e91af2607cc5c7153dd69b1701f3 100644
|
| --- a/src/ia32/lithium-codegen-ia32.cc
|
| +++ b/src/ia32/lithium-codegen-ia32.cc
|
| @@ -5756,6 +5756,45 @@ void LCodeGen::DoClampTToUint8NoSSE2(LClampTToUint8NoSSE2* instr) {
|
| }
|
|
|
|
|
| +void LCodeGen::DoDoubleBits(LDoubleBits* instr) {
|
| + CpuFeatureScope scope(masm(), SSE2);
|
| + XMMRegister value_reg = ToDoubleRegister(instr->value());
|
| + Register result_reg = ToRegister(instr->result());
|
| + if (instr->hydrogen()->bits() == HDoubleBits::HIGH) {
|
| + if (CpuFeatures::IsSupported(SSE4_1)) {
|
| + CpuFeatureScope scope2(masm(), SSE4_1);
|
| + __ pextrd(result_reg, value_reg, 1);
|
| + } else {
|
| + XMMRegister xmm_scratch = double_scratch0();
|
| + __ pshufd(xmm_scratch, value_reg, 1);
|
| + __ movd(result_reg, xmm_scratch);
|
| + }
|
| + } else {
|
| + __ movd(result_reg, value_reg);
|
| + }
|
| +}
|
| +
|
| +
|
| +void LCodeGen::DoConstructDouble(LConstructDouble* instr) {
|
| + Register hi_reg = ToRegister(instr->hi());
|
| + Register lo_reg = ToRegister(instr->lo());
|
| + XMMRegister result_reg = ToDoubleRegister(instr->result());
|
| + CpuFeatureScope scope(masm(), SSE2);
|
| +
|
| + if (CpuFeatures::IsSupported(SSE4_1)) {
|
| + CpuFeatureScope scope2(masm(), SSE4_1);
|
| + __ movd(result_reg, lo_reg);
|
| + __ pinsrd(result_reg, hi_reg, 1);
|
| + } else {
|
| + XMMRegister xmm_scratch = double_scratch0();
|
| + __ movd(result_reg, hi_reg);
|
| + __ psllq(result_reg, 32);
|
| + __ movd(xmm_scratch, lo_reg);
|
| + __ orps(result_reg, xmm_scratch);
|
| + }
|
| +}
|
| +
|
| +
|
| void LCodeGen::DoAllocate(LAllocate* instr) {
|
| class DeferredAllocate V8_FINAL : public LDeferredCode {
|
| public:
|
|
|