Implement optional turbofan UnalignedLoad and UnalignedStore operators

src/mips/macro-assembler-mips.cc

Index: src/mips/macro-assembler-mips.cc
diff --git a/src/mips/macro-assembler-mips.cc b/src/mips/macro-assembler-mips.cc
index 326e757f6180de273d55b3efd74faec556700cef..c0ddae71fe1a5c84b0e4b29f26a92dad0d9b02da 100644
--- a/src/mips/macro-assembler-mips.cc
+++ b/src/mips/macro-assembler-mips.cc
@@ -1162,14 +1162,35 @@ void MacroAssembler::Lsa(Register rd, Register rt, Register rs, uint8_t sa,
 // ------------Pseudo-instructions-------------
 
 void MacroAssembler::Ulw(Register rd, const MemOperand& rs) {
-  lwr(rd, rs);
-  lwl(rd, MemOperand(rs.rm(), rs.offset() + 3));
+  if (is_int16(rs.offset()) && is_int16(rs.offset() + 3)) {
+    if (!rd.is(rs.rm())) {
+      lwr(rd, rs);
+      lwl(rd, MemOperand(rs.rm(), rs.offset() + 3));
+    } else {
+      DCHECK(!rs.rm().is(at));
+      lwr(at, rs);
+      lwl(at, MemOperand(rs.rm(), rs.offset() + 3));
+      mov(rd, at);
+    }
+  } else {  // Offset > 16 bits, use multiple instructions to load.
+    DCHECK(!rd.is(rs.rm()));
+    LoadRegPlusOffsetToAt(rs);
+    lwr(rd, MemOperand(at, 0));
+    lwl(rd, MemOperand(at, 3));
+  }
 }
 
 
 void MacroAssembler::Usw(Register rd, const MemOperand& rs) {
-  swr(rd, rs);
-  swl(rd, MemOperand(rs.rm(), rs.offset() + 3));
+  DCHECK(!rd.is(rs.rm()));
+  if (is_int16(rs.offset()) && is_int16(rs.offset() + 3)) {
+    swr(rd, rs);
+    swl(rd, MemOperand(rs.rm(), rs.offset() + 3));
+  } else {
+    LoadRegPlusOffsetToAt(rs);
+    swr(rd, MemOperand(at, 0));
+    swl(rd, MemOperand(at, 3));
+  }
 }