Implement optional turbofan UnalignedLoad and UnalignedStore operators

src/compiler/mips/code-generator-mips.cc

Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc
index 2c5264e498ee2c33dec148e6125c0b44d37a0165..6d2ef283cd7ae31e5b64dd48620fe8301450bd1b 100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -1163,18 +1163,36 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
     case kMipsLhu:
       __ lhu(i.OutputRegister(), i.MemoryOperand());
       break;
+    case kMipsUlhu:
+      UNREACHABLE();

[Paul Lind, 2016/03/12 05:07:46]

I'm guessing you just don't have implementation yet, and this will be removed?
Seems like the instruction-selector can generate this instruction....

+      __ lhu(i.OutputRegister(), i.MemoryOperand());
+      break;
     case kMipsLh:
       __ lh(i.OutputRegister(), i.MemoryOperand());
       break;
+    case kMipsUlh:
+      UNREACHABLE();
+      __ lh(i.OutputRegister(), i.MemoryOperand());
+      break;
     case kMipsSh:
       __ sh(i.InputRegister(2), i.MemoryOperand());
       break;
+    case kMipsUsh:
+      UNREACHABLE();
+      __ sh(i.InputRegister(2), i.MemoryOperand());
+      break;
     case kMipsLw:
       __ lw(i.OutputRegister(), i.MemoryOperand());
       break;
+    case kMipsUlw:
+      __ Ulw(i.OutputRegister(), i.MemoryOperand());
+      break;
     case kMipsSw:
       __ sw(i.InputRegister(2), i.MemoryOperand());
       break;
+    case kMipsUsw:
+      __ Usw(i.InputRegister(2), i.MemoryOperand());
+      break;
     case kMipsLwc1: {
       __ lwc1(i.OutputSingleRegister(), i.MemoryOperand());
       break;