[wasm] Fixed register allocation for Word32PairShl on arm.

src/compiler/arm/instruction-selector-arm.cc

Index: src/compiler/arm/instruction-selector-arm.cc
diff --git a/src/compiler/arm/instruction-selector-arm.cc b/src/compiler/arm/instruction-selector-arm.cc
index 0e8f30c3bfe8e617351b96ece4ef37cb95e1a83c..2439a8273d95275502bb96995175f8e12bd85ce0 100644
--- a/src/compiler/arm/instruction-selector-arm.cc
+++ b/src/compiler/arm/instruction-selector-arm.cc
@@ -785,6 +785,8 @@ void InstructionSelector::VisitInt32PairAdd(Node* node) {
 
 void InstructionSelector::VisitWord32PairShl(Node* node) {
   ArmOperandGenerator g(this);
+  // We use g.UseUniqueRegister here for InputAt(0) to guarantee that there is
+  // no register aliasing with output registers.
   Int32Matcher m(node->InputAt(2));
   InstructionOperand shift_operand;
   if (m.HasValue()) {
@@ -793,15 +795,15 @@ void InstructionSelector::VisitWord32PairShl(Node* node) {
     shift_operand = g.UseUniqueRegister(m.node());
   }
 
-  InstructionOperand inputs[] = {g.UseRegister(node->InputAt(0)),
+  InstructionOperand inputs[] = {g.UseUniqueRegister(node->InputAt(0)),
                                  g.UseRegister(node->InputAt(1)),
                                  shift_operand};
 
   InstructionOperand outputs[] = {
-      g.DefineSameAsFirst(node),
+      g.DefineAsRegister(node),
       g.DefineAsRegister(NodeProperties::FindProjection(node, 1))};
 
-  Emit(kArmPairLsl, 2, outputs, 3, inputs);
+  Emit(kArmLslPair, 2, outputs, 3, inputs);
 }
 
 void InstructionSelector::VisitWord32PairShr(Node* node) { UNIMPLEMENTED(); }