[wasm] Fixed register allocation for Word32PairShl on arm.

src/arm/macro-assembler-arm.cc

Index: src/arm/macro-assembler-arm.cc
diff --git a/src/arm/macro-assembler-arm.cc b/src/arm/macro-assembler-arm.cc
index 907548d4588bdc2123a943a8da9755ef44a8eed7..b1df77f9d7e14bdfedb7b7a7e789a471620239b7 100644
--- a/src/arm/macro-assembler-arm.cc
+++ b/src/arm/macro-assembler-arm.cc
@@ -1101,15 +1101,16 @@ void MacroAssembler::VmovLow(DwVfpRegister dst, Register src) {
     vmov(dst, VmovIndexLo, src);
   }
 }
-void MacroAssembler::PairLsl(Register dst_low, Register dst_high,
+void MacroAssembler::LslPair(Register dst_low, Register dst_high,
                              Register src_low, Register src_high,
                              Register scratch, Register shift) {
-  DCHECK(!AreAliased(dst_low, src_high, shift));
-  DCHECK(!AreAliased(dst_high, src_low, shift));
+  DCHECK(!AreAliased(dst_high, src_low));
+  DCHECK(!AreAliased(dst_high, shift));
+
   Label less_than_32;
   Label done;
-  cmp_raw_immediate(shift, 32);
-  b(lt, &less_than_32);
+  rsb(scratch, shift, Operand(32), SetCC);
+  b(gt, &less_than_32);
   // If shift >= 32
   and_(scratch, shift, Operand(0x1f));
   lsl(dst_high, src_low, Operand(scratch));
@@ -1117,27 +1118,28 @@ void MacroAssembler::PairLsl(Register dst_low, Register dst_high,
   jmp(&done);
   bind(&less_than_32);
   // If shift < 32
-  rsb(scratch, shift, Operand(32));
   lsl(dst_high, src_high, Operand(shift));
   orr(dst_high, dst_high, Operand(src_low, LSR, scratch));
   lsl(dst_low, src_low, Operand(shift));
   bind(&done);
 }
 
-void MacroAssembler::PairLsl(Register dst_low, Register dst_high,
+void MacroAssembler::LslPair(Register dst_low, Register dst_high,
                              Register src_low, Register src_high,
                              uint32_t shift) {
-  DCHECK(!AreAliased(dst_low, src_high));
   DCHECK(!AreAliased(dst_high, src_low));
   Label less_than_32;
   Label done;
-  if (shift >= 32) {
+  if (shift == 0) {
+    Move(dst_high, src_high);
+    Move(dst_low, src_low);
+  } else if (shift == 32) {
+    Move(dst_high, src_low);
+    Move(dst_low, Operand(0));
+  } else if (shift >= 32) {
     shift &= 0x1f;
     lsl(dst_high, src_low, Operand(shift));
     mov(dst_low, Operand(0));
-  } else if (shift == 0) {
-    Move(dst_low, src_low);
-    Move(dst_high, src_high);
   } else {
     lsl(dst_high, src_high, Operand(shift));
     orr(dst_high, dst_high, Operand(src_low, LSR, 32 - shift));