[wasm] Fixed register allocation for Word32PairShl on arm.

src/arm/macro-assembler-arm.cc

 // Copyright 2012 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include <limits.h>  // For LONG_MIN, LONG_MAX.
 
 #if V8_TARGET_ARCH_ARM
 
 #include "src/base/bits.h"
 #include "src/base/division-by-constant.h"
@@ skipping 1083 matching lines @@
 
 
 void MacroAssembler::VmovLow(DwVfpRegister dst, Register src) {
   if (dst.code() < 16) {
     const LowDwVfpRegister loc = LowDwVfpRegister::from_code(dst.code());
     vmov(loc.low(), src);
   } else {
     vmov(dst, VmovIndexLo, src);
   }
 }
-void MacroAssembler::PairLsl(Register dst_low, Register dst_high,
+void MacroAssembler::LslPair(Register dst_low, Register dst_high,
                              Register src_low, Register src_high,
                              Register scratch, Register shift) {
-  DCHECK(!AreAliased(dst_low, src_high, shift));
-  DCHECK(!AreAliased(dst_high, src_low, shift));
+  DCHECK(!AreAliased(dst_high, src_low));
+  DCHECK(!AreAliased(dst_high, shift));
+
   Label less_than_32;
   Label done;
-  cmp_raw_immediate(shift, 32);
-  b(lt, &less_than_32);
+  rsb(scratch, shift, Operand(32), SetCC);
+  b(gt, &less_than_32);
   // If shift >= 32
   and_(scratch, shift, Operand(0x1f));
   lsl(dst_high, src_low, Operand(scratch));
   mov(dst_low, Operand(0));
   jmp(&done);
   bind(&less_than_32);
   // If shift < 32
-  rsb(scratch, shift, Operand(32));
   lsl(dst_high, src_high, Operand(shift));
   orr(dst_high, dst_high, Operand(src_low, LSR, scratch));
   lsl(dst_low, src_low, Operand(shift));
   bind(&done);
 }
 
-void MacroAssembler::PairLsl(Register dst_low, Register dst_high,
+void MacroAssembler::LslPair(Register dst_low, Register dst_high,
                              Register src_low, Register src_high,
                              uint32_t shift) {
-  DCHECK(!AreAliased(dst_low, src_high));
   DCHECK(!AreAliased(dst_high, src_low));
   Label less_than_32;
   Label done;
-  if (shift >= 32) {
+  if (shift == 0) {
+    Move(dst_high, src_high);
+    Move(dst_low, src_low);
+  } else if (shift == 32) {
+    Move(dst_high, src_low);
+    Move(dst_low, Operand(0));
+  } else if (shift >= 32) {
     shift &= 0x1f;
     lsl(dst_high, src_low, Operand(shift));
     mov(dst_low, Operand(0));
-  } else if (shift == 0) {
-    Move(dst_low, src_low);
-    Move(dst_high, src_high);
   } else {
     lsl(dst_high, src_high, Operand(shift));
     orr(dst_high, dst_high, Operand(src_low, LSR, 32 - shift));
     lsl(dst_low, src_low, Operand(shift));
   }
 }
 
 void MacroAssembler::LoadConstantPoolPointerRegisterFromCodeTargetAddress(
     Register code_target_address) {
   DCHECK(FLAG_enable_embedded_constant_pool);
@@ skipping 2685 matching lines @@
     }
   }
   if (mag.shift > 0) mov(result, Operand(result, ASR, mag.shift));
   add(result, result, Operand(dividend, LSR, 31));
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_ARM