Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(231)

Issues Search
    My Issues | Starred     Open | Closed | All

Unified Diff: tests_lit/llvm2ice_tests/64bit.pnacl.ll

Issue 1745393002: Subzero. ARM32. Reverts cl 1687553002. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Created 4 years, 10 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
« no previous file with comments | « tests_lit/assembler/arm32/vpush.ll ('k') | tests_lit/llvm2ice_tests/alloc.ll » ('j') | no next file with comments »
Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
Index: tests_lit/llvm2ice_tests/64bit.pnacl.ll
diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index 4106d3c44a7806316c4418aa1a12d21e14d6ee3a..a818b2ad9d45149e36d9534806b7ac3452775bae 100644
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -10,15 +10,18 @@
; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
; RUN: | %if --need=target_X8632 --command FileCheck --check-prefix=OPTM1 %s
+; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
+; once enough infrastructure is in. Also, switch to --filetype=obj
+; when possible.
; RUN: %if --need=target_ARM32 --need=allow_dump \
-; RUN: --command %p2i --filetype=obj --assemble \
-; RUN: --disassemble --target arm32 -i %s --args -O2 \
+; RUN: --command %p2i --filetype=asm --assemble \
+; RUN: --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \
; RUN: -allow-externally-defined-symbols \
; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-O2 %s
; RUN: %if --need=target_ARM32 --need=allow_dump \
-; RUN: --command %p2i --filetype=obj --assemble --disassemble --target arm32 \
-; RUN: -i %s --args -Om1 \
+; RUN: --command %p2i --filetype=asm --assemble --disassemble --target arm32 \
+; RUN: -i %s --args -Om1 --skip-unimplemented \
; RUN: -allow-externally-defined-symbols \
; RUN: | %if --need=target_ARM32 --need=allow_dump \
; RUN: --command FileCheck --check-prefix ARM32 --check-prefix ARM32-OM1 %s
@@ -99,24 +102,18 @@ entry:
; ARM32-LABEL: pass64BitArg
; ARM32: str {{.*}}, [sp]
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
-; ARM32: movt [[CALL]], {{.+}} ignore64BitArgNoInline
; ARM32: mov r2, #123
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} ignore64BitArgNoInline
; ARM32: str {{.*}}, [sp]
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
-; ARM32: movt [[CALL]], {{.+}} ignore64BitArgNoInline
; ARM32: {{mov|ldr}} r0
; ARM32: {{mov|ldr}} r1
; ARM32: mov r2, #123
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} ignore64BitArgNoInline
; ARM32: str {{.*}}, [sp]
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
-; ARM32: movt [[CALL]], {{.+}} ignore64BitArgNoInline
; ARM32: {{mov|ldr}} r0
; ARM32: {{mov|ldr}} r1
; ARM32: mov r2, #123
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} ignore64BitArgNoInline
; MIPS32-LABEL: pass64BitArg
@@ -158,13 +155,10 @@ entry:
; ARM32: movt [[REG2]], {{.*}} ; 0x1234
; ARM32: str [[REG1]], [sp, #4]
; ARM32: str [[REG2]], [sp]
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
-; ARM32: movt [[CALL]], {{.+}} ignore64BitArgNoInline
; ARM32: {{mov|ldr}} r0
; ARM32: {{mov|ldr}} r1
; ARM32: mov r2, #123
-; ARM32: blx [[CALL]]
-
+; ARM32: bl {{.*}} ignore64BitArgNoInline
define internal i32 @pass64BitUndefArg() {
entry:
@@ -185,10 +179,8 @@ entry:
; ARM32: sub sp
; ARM32: mov {{.*}}, #0
; ARM32: str
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
-; ARM32: movt [[CALL]], {{.+}} ignore64BitArgNoInline
; ARM32: mov {{.*}}, #123
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} ignore64BitArgNoInline
; MIPS32-LABEL: pass64BitUndefArg
; MIPS32: jr ra
@@ -414,9 +406,7 @@ entry:
; ARM32-LABEL: div64BitSigned
; ARM32: orrs {{r.*}}, {{r.*}}
; ARM32: bne
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} __divdi3
-; ARM32: movt [[CALL]], {{.+}} __divdi3
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} __divdi3
define internal i64 @div64BitSignedConst(i64 %a) {
entry:
@@ -436,12 +426,10 @@ entry:
; ARM32-LABEL: div64BitSignedConst
; For a constant, we should be able to optimize-out the divide by zero check.
; ARM32-NOT: orrs
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} __divdi3
-; ARM32: movt [[CALL]], {{.+}} __divdi3
; ARM32: movw {{.*}} ; 0x2ff2
; ARM32: movt {{.*}} ; 0x73ce
; ARM32: movw {{.*}} ; 0xb3a
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} __divdi3
define internal i64 @div64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -457,9 +445,7 @@ entry:
; ARM32-LABEL: div64BitUnsigned
; ARM32: orrs {{r.*}}, {{r.*}}
; ARM32: bne
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} __udivdi3
-; ARM32: movt [[CALL]], {{.+}} __udivdi3
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} __udivdi3
define internal i64 @rem64BitSigned(i64 %a, i64 %b) {
entry:
@@ -475,9 +461,7 @@ entry:
; ARM32-LABEL: rem64BitSigned
; ARM32: orrs {{r.*}}, {{r.*}}
; ARM32: bne
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} __moddi3
-; ARM32: movt [[CALL]], {{.+}} __moddi3
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} __moddi3
define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) {
entry:
@@ -493,9 +477,7 @@ entry:
; ARM32-LABEL: rem64BitUnsigned
; ARM32: orrs {{r.*}}, {{r.*}}
; ARM32: bne
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} __umoddi3
-; ARM32: movt [[CALL]], {{.+}} __umoddi3
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} __umoddi3
define internal i64 @shl64BitSigned(i64 %a, i64 %b) {
entry:
@@ -1158,16 +1140,12 @@ if.end3: ; preds = %if.then2, %if.end
; ARM32: cmpeq
; ARM32-OM1: tst
; ARM32: bne
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} func
-; ARM32: movt [[CALL]], {{.+}} func
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} <func>
; ARM32: cmp
; ARM32: cmpeq
; ARM32-OM1: tst
; ARM32: bne
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} func
-; ARM32: movt [[CALL]], {{.+}} func
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} <func>
; ARM32: bx
declare void @func()
@@ -1232,9 +1210,7 @@ if.end3: ; preds = %if.end, %if.then2
; ARM32-OM1: tst
; ARM32-OM1: bne
; ARM32-O2: beq
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} func
-; ARM32: movt [[CALL]], {{.+}} func
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} <func>
; ARM32: cmp
; ARM32: cmpeq
; ARM32-OM1: tst
« no previous file with comments | « tests_lit/assembler/arm32/vpush.ll ('k') | tests_lit/llvm2ice_tests/alloc.ll » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698