Subzero. ARM32. Reverts cl 1687553002.

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck --check-prefix=OPTM1 %s
 
+; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
+; once enough infrastructure is in. Also, switch to --filetype=obj
+; when possible.
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
-; RUN:   --command %p2i --filetype=obj --assemble \
-; RUN:   --disassemble --target arm32 -i %s --args -O2 \
+; RUN:   --command %p2i --filetype=asm --assemble \
+; RUN:   --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix ARM32 --check-prefix ARM32-O2 %s
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
-; RUN:   --command %p2i --filetype=obj --assemble --disassemble --target arm32 \
-; RUN:   -i %s --args -Om1 \
+; RUN:   --command %p2i --filetype=asm --assemble --disassemble --target arm32 \
+; RUN:   -i %s --args -Om1 --skip-unimplemented \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix ARM32 --check-prefix ARM32-OM1 %s
 
 ; TODO(rkotler): Stop skipping unimplemented parts (via --skip-unimplemented)
 ; once enough infrastructure is in. Also, switch to --filetype=obj
 ; when possible.
 ; RUN: %if --need=target_MIPS32 --need=allow_dump \
 ; RUN:   --command %p2i --filetype=asm --assemble \
 ; RUN:   --disassemble --target mips32 -i %s --args -O2 --skip-unimplemented \
@@ skipping 60 matching lines @@
 ; OPTM1:      call {{.*}} R_{{.*}}    ignore64BitArgNoInline
 ; OPTM1:      mov     DWORD PTR [esp+0x4]
 ; OPTM1:      mov     DWORD PTR [esp]
 ; OPTM1:      mov     DWORD PTR [esp+0x8],0x7b
 ; OPTM1:      mov     DWORD PTR [esp+0x10]
 ; OPTM1:      mov     DWORD PTR [esp+0xc]
 ; OPTM1:      call {{.*}} R_{{.*}}    ignore64BitArgNoInline
 
 ; ARM32-LABEL: pass64BitArg
 ; ARM32:      str     {{.*}}, [sp]
-; ARM32:      movw    [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
-; ARM32:      movt    [[CALL]], {{.+}} ignore64BitArgNoInline
 ; ARM32:      mov     r2, #123
-; ARM32:      blx     [[CALL]]
+; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      str     {{.*}}, [sp]
-; ARM32:      movw    [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
-; ARM32:      movt    [[CALL]], {{.+}} ignore64BitArgNoInline
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      mov     r2, #123
-; ARM32:      blx     [[CALL]]
+; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      str     {{.*}}, [sp]
-; ARM32:      movw    [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
-; ARM32:      movt    [[CALL]], {{.+}} ignore64BitArgNoInline
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      mov     r2, #123
-; ARM32:      blx      [[CALL]]
+; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 
 ; MIPS32-LABEL: pass64BitArg
 
 
 declare i32 @ignore64BitArgNoInline(i64, i32, i64)
 
 define internal i32 @pass64BitConstArg(i64 %a, i64 %b) {
 entry:
   %call = call i32 @ignore64BitArgNoInline(i64 %b, i32 123, i64 -2401053092306725256)
   ret i32 %call
@@ skipping 21 matching lines @@
 ; OPTM1-NOT:  mov
 ; OPTM1:      call {{.*}} R_{{.*}}    ignore64BitArgNoInline
 
 ; ARM32-LABEL: pass64BitConstArg
 ; ARM32:      movw    [[REG1:r.*]], {{.*}} ; 0xbeef
 ; ARM32:      movt    [[REG1]], {{.*}}     ; 0xdead
 ; ARM32:      movw    [[REG2:r.*]], {{.*}} ; 0x5678
 ; ARM32:      movt    [[REG2]], {{.*}}     ; 0x1234
 ; ARM32:      str     [[REG1]], [sp, #4]
 ; ARM32:      str     [[REG2]], [sp]
-; ARM32:      movw    [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
-; ARM32:      movt    [[CALL]], {{.+}} ignore64BitArgNoInline
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      mov     r2, #123
-; ARM32:      blx     [[CALL]]
-
+; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 
 define internal i32 @pass64BitUndefArg() {
 entry:
   %call = call i32 @ignore64BitArgNoInline(i64 0, i32 123, i64 undef)
   ret i32 %call
 }
 ; CHECK-LABEL: pass64BitUndefArg
 ; CHECK: sub esp
 ; CHECK: mov DWORD PTR{{.*}},0x7b
 ; CHECK: mov DWORD PTR{{.*}},0x0
 ; CHECK: call {{.*}} R_{{.*}} ignore64BitArgNoInline
 ; OPTM1-LABEL: pass64BitUndefArg
 ; OPTM1: sub esp
 ; OPTM1: mov DWORD PTR{{.*}},0x7b
 ; OPTM1: mov DWORD PTR{{.*}},0x0
 ; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
 ; ARM32-LABEL: pass64BitUndefArg
 ; ARM32: sub sp
 ; ARM32: mov {{.*}}, #0
 ; ARM32: str
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} ignore64BitArgNoInline
-; ARM32: movt [[CALL]], {{.+}} ignore64BitArgNoInline
 ; ARM32: mov {{.*}}, #123
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} ignore64BitArgNoInline
 
 ; MIPS32-LABEL: pass64BitUndefArg
 ; MIPS32: jr  ra
 
 define internal i64 @return64BitArg(i64 %padding, i64 %a) {
 entry:
   ret i64 %a
 }
 ; CHECK-LABEL: return64BitArg
 ; CHECK: mov     {{.*}},DWORD PTR [esp+0xc]
@@ skipping 205 matching lines @@
 }
 ; CHECK-LABEL: div64BitSigned
 ; CHECK: call {{.*}} R_{{.*}}    __divdi3
 
 ; OPTM1-LABEL: div64BitSigned
 ; OPTM1: call {{.*}} R_{{.*}}    __divdi3
 ;
 ; ARM32-LABEL: div64BitSigned
 ; ARM32: orrs {{r.*}}, {{r.*}}
 ; ARM32: bne
-; ARM32: movw   [[CALL:r[0-9]]], {{.+}} __divdi3
-; ARM32: movt   [[CALL]], {{.+}} __divdi3
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} __divdi3
 
 define internal i64 @div64BitSignedConst(i64 %a) {
 entry:
   %div = sdiv i64 %a, 12345678901234
   ret i64 %div
 }
 ; CHECK-LABEL: div64BitSignedConst
 ; CHECK: mov     DWORD PTR [esp+0xc],0xb3a
 ; CHECK: mov     DWORD PTR [esp+0x8],0x73ce2ff2
 ; CHECK: call {{.*}} R_{{.*}}    __divdi3
 ;
 ; OPTM1-LABEL: div64BitSignedConst
 ; OPTM1: mov     DWORD PTR [esp+0xc],0xb3a
 ; OPTM1: mov     DWORD PTR [esp+0x8],0x73ce2ff2
 ; OPTM1: call {{.*}} R_{{.*}}    __divdi3
 ;
 ; ARM32-LABEL: div64BitSignedConst
 ; For a constant, we should be able to optimize-out the divide by zero check.
 ; ARM32-NOT: orrs
-; ARM32: movw   [[CALL:r[0-9]]], {{.+}} __divdi3
-; ARM32: movt   [[CALL]], {{.+}} __divdi3
 ; ARM32: movw {{.*}} ; 0x2ff2
 ; ARM32: movt {{.*}} ; 0x73ce
 ; ARM32: movw {{.*}} ; 0xb3a
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} __divdi3
 
 define internal i64 @div64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %div = udiv i64 %a, %b
   ret i64 %div
 }
 ; CHECK-LABEL: div64BitUnsigned
 ; CHECK: call {{.*}} R_{{.*}}    __udivdi3
 ;
 ; OPTM1-LABEL: div64BitUnsigned
 ; OPTM1: call {{.*}} R_{{.*}}    __udivdi3
 ;
 ; ARM32-LABEL: div64BitUnsigned
 ; ARM32: orrs {{r.*}}, {{r.*}}
 ; ARM32: bne
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} __udivdi3
-; ARM32: movt [[CALL]], {{.+}} __udivdi3
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} __udivdi3
 
 define internal i64 @rem64BitSigned(i64 %a, i64 %b) {
 entry:
   %rem = srem i64 %a, %b
   ret i64 %rem
 }
 ; CHECK-LABEL: rem64BitSigned
 ; CHECK: call {{.*}} R_{{.*}}    __moddi3
 ;
 ; OPTM1-LABEL: rem64BitSigned
 ; OPTM1: call {{.*}} R_{{.*}}    __moddi3
 ;
 ; ARM32-LABEL: rem64BitSigned
 ; ARM32: orrs {{r.*}}, {{r.*}}
 ; ARM32: bne
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} __moddi3
-; ARM32: movt [[CALL]], {{.+}} __moddi3
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} __moddi3
 
 define internal i64 @rem64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %rem = urem i64 %a, %b
   ret i64 %rem
 }
 ; CHECK-LABEL: rem64BitUnsigned
 ; CHECK: call {{.*}} R_{{.*}}    __umoddi3
 ;
 ; OPTM1-LABEL: rem64BitUnsigned
 ; OPTM1: call {{.*}} R_{{.*}}    __umoddi3
 ;
 ; ARM32-LABEL: rem64BitUnsigned
 ; ARM32: orrs {{r.*}}, {{r.*}}
 ; ARM32: bne
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} __umoddi3
-; ARM32: movt [[CALL]], {{.+}} __umoddi3
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} __umoddi3
 
 define internal i64 @shl64BitSigned(i64 %a, i64 %b) {
 entry:
   %shl = shl i64 %a, %b
   ret i64 %shl
 }
 ; CHECK-LABEL: shl64BitSigned
 ; CHECK: shld
 ; CHECK: shl e
 ; CHECK: test {{.*}},0x20
@@ skipping 642 matching lines @@
 ; OPTM1-NEXT: cmp [[RESULT]],0x0
 ; OPTM1-NEXT: jne
 ; OPTM1-NEXT: jmp
 ; OPTM1-NEXT: call
 
 ; ARM32-LABEL: icmpEq64
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32-OM1: tst
 ; ARM32: bne
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} func
-; ARM32: movt [[CALL]], {{.+}} func
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} <func>
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32-OM1: tst
 ; ARM32: bne
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} func
-; ARM32: movt [[CALL]], {{.+}} func
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} <func>
 ; ARM32: bx
 
 declare void @func()
 
 define internal void @icmpNe64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ne i64 %a, %b
   br i1 %cmp, label %if.then, label %if.end
 
 if.then:                                          ; preds = %entry
@@ skipping 44 matching lines @@
 ; OPTM1-NEXT: jne {{.*}}
 ; OPTM1-NEXT: jmp {{.*}}
 ; OPTM1-NEXT: call
 
 ; ARM32-LABEL: icmpNe64
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32-OM1: tst
 ; ARM32-OM1: bne
 ; ARM32-O2: beq
-; ARM32: movw [[CALL:r[0-9]]], {{.+}} func
-; ARM32: movt [[CALL]], {{.+}} func
-; ARM32: blx [[CALL]]
+; ARM32: bl {{.*}} <func>
 ; ARM32: cmp
 ; ARM32: cmpeq
 ; ARM32-OM1: tst
 ; ARM32-OM1: bne
 ; ARM32-O2: beq
 ; ARM32: bl
 
 define internal void @icmpGt64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %cmp = icmp ugt i64 %a, %b
@@ skipping 723 matching lines @@
 
 ; CHECK-LABEL: phi64Undef
 ; CHECK: mov {{.*}},0x0
 ; CHECK: mov {{.*}},0x0
 ; OPTM1-LABEL: phi64Undef
 ; OPTM1: mov {{.*}},0x0
 ; OPTM1: mov {{.*}},0x0
 ; ARM32-LABEL: phi64Undef
 ; ARM32: mov {{.*}} #0
 ; ARM32: mov {{.*}} #0