Enable concurrent sweep on MIPS and ARM64.

runtime/vm/constants_arm64.h

Index: runtime/vm/constants_arm64.h
diff --git a/runtime/vm/constants_arm64.h b/runtime/vm/constants_arm64.h
index 913a69c89c41435860f4f3e4da49261cfeabf2ec..7a0a18b0a7c43d5a19fa0c6ce6f6c378e6ad4a4d 100644
--- a/runtime/vm/constants_arm64.h
+++ b/runtime/vm/constants_arm64.h
@@ -330,6 +330,8 @@ enum SystemOp {
   SystemMask = 0xffc00000,
   SystemFixed = CompareBranchFixed | B31 | B30 | B24,
   HINT = SystemFixed | B17 | B16 | B13 | B4 | B3 | B2 | B1 | B0,
+  CLREX = SystemFixed | B17 | B16 | B13 | B12 | B11 | B10 | B9 | B8 |
+      B6 | B4 | B3 | B2 | B1 | B0,
 };
 
 // C3.2.5
@@ -364,6 +366,14 @@ enum LoadRegLiteralOp {
   LDRpc = LoadRegLiteralFixed,
 };
 
+// C3.3.6
+enum LoadStoreExclusiveOp {
+  LoadStoreExclusiveMask = 0x3f000000,
+  LoadStoreExclusiveFixed = B27,
+  LDXR = LoadStoreExclusiveFixed | B22,
+  STXR = LoadStoreExclusiveFixed,
+};
+
 // C3.3.7-10
 enum LoadStoreRegOp {
   LoadStoreRegMask = 0x3a000000,
@@ -616,6 +626,7 @@ _V(UnconditionalBranchReg)                                                     \
 _V(LoadStoreReg)                                                               \
 _V(LoadStoreRegPair)                                                           \
 _V(LoadRegLiteral)                                                             \
+_V(LoadStoreExclusive)                                                         \
 _V(AddSubImm)                                                                  \
 _V(LogicalImm)                                                                 \
 _V(MoveWide)                                                                   \
@@ -692,6 +703,8 @@ enum InstructionFields {
   kRtBits = 5,
   kRt2Shift = 10,
   kRt2Bits = 5,
+  kRsShift = 16,
+  kRsBits = 5,
 
   // V Registers.
   kVdShift = 0,
@@ -892,6 +905,8 @@ class Instr {
                                         Bits(kRtShift, kRtBits)); }
   inline Register Rt2Field() const { return static_cast<Register>(
                                         Bits(kRt2Shift, kRt2Bits)); }
+  inline Register RsField() const { return static_cast<Register>(
+                                        Bits(kRsShift, kRsBits)); }
 
   inline VRegister VdField() const { return static_cast<VRegister>(
                                         Bits(kVdShift, kVdBits)); }