Enable concurrent sweep on MIPS and ARM64.

runtime/vm/constants_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_CONSTANTS_ARM64_H_
 #define VM_CONSTANTS_ARM64_H_
 
 #include "platform/assert.h"
 
 namespace dart {
@@ skipping 312 matching lines @@
   SVC = ExceptionGenFixed | B0,
   BRK = ExceptionGenFixed | B21,
   HLT = ExceptionGenFixed | B22,
 };
 
 // C3.2.4
 enum SystemOp {
   SystemMask = 0xffc00000,
   SystemFixed = CompareBranchFixed | B31 | B30 | B24,
   HINT = SystemFixed | B17 | B16 | B13 | B4 | B3 | B2 | B1 | B0,
+  CLREX = SystemFixed | B17 | B16 | B13 | B12 | B11 | B10 | B9 | B8 |
+      B6 | B4 | B3 | B2 | B1 | B0,
 };
 
 // C3.2.5
 enum TestAndBranchOp {
   TestAndBranchMask = 0x7e000000,
   TestAndBranchFixed = CompareBranchFixed | B29 | B25,
   TBZ = TestAndBranchFixed,
   TBNZ = TestAndBranchFixed | B24,
 };
 
@@ skipping 14 matching lines @@
   RET = BR | B22,
 };
 
 // C3.3.5
 enum LoadRegLiteralOp {
   LoadRegLiteralMask = 0x3b000000,
   LoadRegLiteralFixed = LoadStoreFixed | B28,
   LDRpc = LoadRegLiteralFixed,
 };
 
+// C3.3.6
+enum LoadStoreExclusiveOp {
+  LoadStoreExclusiveMask = 0x3f000000,
+  LoadStoreExclusiveFixed = B27,
+  LDXR = LoadStoreExclusiveFixed | B22,
+  STXR = LoadStoreExclusiveFixed,
+};
+
 // C3.3.7-10
 enum LoadStoreRegOp {
   LoadStoreRegMask = 0x3a000000,
   LoadStoreRegFixed = LoadStoreFixed | B29 | B28,
   STR = LoadStoreRegFixed,
   LDR = LoadStoreRegFixed | B22,
   LDRS = LoadStoreRegFixed | B23,
   FSTR = STR | B26,
   FLDR = LDR | B26,
   FSTRQ = STR | B26 | B23,
@@ skipping 232 matching lines @@
 _V(CompareAndBranch)                                                           \
 _V(ConditionalBranch)                                                          \
 _V(ExceptionGen)                                                               \
 _V(System)                                                                     \
 _V(TestAndBranch)                                                              \
 _V(UnconditionalBranch)                                                        \
 _V(UnconditionalBranchReg)                                                     \
 _V(LoadStoreReg)                                                               \
 _V(LoadStoreRegPair)                                                           \
 _V(LoadRegLiteral)                                                             \
+_V(LoadStoreExclusive)                                                         \
 _V(AddSubImm)                                                                  \
 _V(LogicalImm)                                                                 \
 _V(MoveWide)                                                                   \
 _V(PCRel)                                                                      \
 _V(AddSubShiftExt)                                                             \
 _V(AddSubWithCarry)                                                            \
 _V(ConditionalSelect)                                                          \
 _V(MiscDP1Source)                                                              \
 _V(MiscDP2Source)                                                              \
 _V(MiscDP3Source)                                                              \
@@ skipping 56 matching lines @@
   kRnShift = 5,
   kRnBits = 5,
   kRaShift = 10,
   kRaBits = 5,
   kRmShift = 16,
   kRmBits = 5,
   kRtShift = 0,
   kRtBits = 5,
   kRt2Shift = 10,
   kRt2Bits = 5,
+  kRsShift = 16,
+  kRsBits = 5,
 
   // V Registers.
   kVdShift = 0,
   kVdBits = 5,
   kVnShift = 5,
   kVnBits = 5,
   kVmShift = 16,
   kVmBits = 5,
   kVtShift = 0,
   kVtBits = 5,
@@ skipping 180 matching lines @@
   inline Register RnField() const { return static_cast<Register>(
                                         Bits(kRnShift, kRnBits)); }
   inline Register RaField() const { return static_cast<Register>(
                                         Bits(kRaShift, kRaBits)); }
   inline Register RmField() const { return static_cast<Register>(
                                         Bits(kRmShift, kRmBits)); }
   inline Register RtField() const { return static_cast<Register>(
                                         Bits(kRtShift, kRtBits)); }
   inline Register Rt2Field() const { return static_cast<Register>(
                                         Bits(kRt2Shift, kRt2Bits)); }
+  inline Register RsField() const { return static_cast<Register>(
+                                        Bits(kRsShift, kRsBits)); }
 
   inline VRegister VdField() const { return static_cast<VRegister>(
                                         Bits(kVdShift, kVdBits)); }
   inline VRegister VnField() const { return static_cast<VRegister>(
                                         Bits(kVnShift, kVnBits)); }
   inline VRegister VmField() const { return static_cast<VRegister>(
                                         Bits(kVmShift, kVmBits)); }
   inline VRegister VtField() const { return static_cast<VRegister>(
                                         Bits(kVtShift, kVtBits)); }
 
@@ skipping 169 matching lines @@
   static Instr* At(uword pc) { return reinterpret_cast<Instr*>(pc); }
 
  private:
   DISALLOW_ALLOCATION();
   DISALLOW_IMPLICIT_CONSTRUCTORS(Instr);
 };
 
 }  // namespace dart
 
 #endif  // VM_CONSTANTS_ARM64_H_