Enable concurrent sweep on MIPS and ARM64.

runtime/vm/assembler_mips.h

Index: runtime/vm/assembler_mips.h
diff --git a/runtime/vm/assembler_mips.h b/runtime/vm/assembler_mips.h
index 5cef8b6430d262ed952c1dbf4225f0197b3fac71..1654ac9a0480998f205bcc613eeee58308e7ef48 100644
--- a/runtime/vm/assembler_mips.h
+++ b/runtime/vm/assembler_mips.h
@@ -663,6 +663,10 @@ class Assembler : public ValueObject {
     EmitLoadStore(LHU, rt, addr);
   }
 
+  void ll(Register rt, const Address& addr) {
+    EmitLoadStore(LL, rt, addr);
+  }
+
   void lui(Register rt, const Immediate& imm) {
     ASSERT(Utils::IsUint(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
@@ -791,6 +795,11 @@ class Assembler : public ValueObject {
     EmitLoadStore(SB, rt, addr);
   }
 
+  // rt = 1 on success, 0 on failure.
+  void sc(Register rt, const Address& addr) {
+    EmitLoadStore(SC, rt, addr);
+  }
+
   void sdc1(DRegister dt, const Address& addr) {
     FRegister ft = static_cast<FRegister>(dt * 2);
     EmitFpuLoadStore(SDC1, ft, addr);