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Side by Side Diff: runtime/vm/assembler_mips.h

Issue 1722013002: Enable concurrent sweep on MIPS and ARM64. (Closed) Base URL: git@github.com:dart-lang/sdk.git@master
Patch Set: clrex and assembler tests Created 4 years, 10 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 4
5 #ifndef VM_ASSEMBLER_MIPS_H_ 5 #ifndef VM_ASSEMBLER_MIPS_H_
6 #define VM_ASSEMBLER_MIPS_H_ 6 #define VM_ASSEMBLER_MIPS_H_
7 7
8 #ifndef VM_ASSEMBLER_H_ 8 #ifndef VM_ASSEMBLER_H_
9 #error Do not include assembler_mips.h directly; use assembler.h instead. 9 #error Do not include assembler_mips.h directly; use assembler.h instead.
10 #endif 10 #endif
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656 } 656 }
657 657
658 void lh(Register rt, const Address& addr) { 658 void lh(Register rt, const Address& addr) {
659 EmitLoadStore(LH, rt, addr); 659 EmitLoadStore(LH, rt, addr);
660 } 660 }
661 661
662 void lhu(Register rt, const Address& addr) { 662 void lhu(Register rt, const Address& addr) {
663 EmitLoadStore(LHU, rt, addr); 663 EmitLoadStore(LHU, rt, addr);
664 } 664 }
665 665
666 void ll(Register rt, const Address& addr) {
667 EmitLoadStore(LL, rt, addr);
668 }
669
666 void lui(Register rt, const Immediate& imm) { 670 void lui(Register rt, const Immediate& imm) {
667 ASSERT(Utils::IsUint(kImmBits, imm.value())); 671 ASSERT(Utils::IsUint(kImmBits, imm.value()));
668 const uint16_t imm_value = static_cast<uint16_t>(imm.value()); 672 const uint16_t imm_value = static_cast<uint16_t>(imm.value());
669 EmitIType(LUI, R0, rt, imm_value); 673 EmitIType(LUI, R0, rt, imm_value);
670 } 674 }
671 675
672 void lw(Register rt, const Address& addr) { 676 void lw(Register rt, const Address& addr) {
673 EmitLoadStore(LW, rt, addr); 677 EmitLoadStore(LW, rt, addr);
674 } 678 }
675 679
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784 void ori(Register rt, Register rs, const Immediate& imm) { 788 void ori(Register rt, Register rs, const Immediate& imm) {
785 ASSERT(Utils::IsUint(kImmBits, imm.value())); 789 ASSERT(Utils::IsUint(kImmBits, imm.value()));
786 const uint16_t imm_value = static_cast<uint16_t>(imm.value()); 790 const uint16_t imm_value = static_cast<uint16_t>(imm.value());
787 EmitIType(ORI, rs, rt, imm_value); 791 EmitIType(ORI, rs, rt, imm_value);
788 } 792 }
789 793
790 void sb(Register rt, const Address& addr) { 794 void sb(Register rt, const Address& addr) {
791 EmitLoadStore(SB, rt, addr); 795 EmitLoadStore(SB, rt, addr);
792 } 796 }
793 797
798 // rt = 1 on success, 0 on failure.
799 void sc(Register rt, const Address& addr) {
800 EmitLoadStore(SC, rt, addr);
801 }
802
794 void sdc1(DRegister dt, const Address& addr) { 803 void sdc1(DRegister dt, const Address& addr) {
795 FRegister ft = static_cast<FRegister>(dt * 2); 804 FRegister ft = static_cast<FRegister>(dt * 2);
796 EmitFpuLoadStore(SDC1, ft, addr); 805 EmitFpuLoadStore(SDC1, ft, addr);
797 } 806 }
798 807
799 void sh(Register rt, const Address& addr) { 808 void sh(Register rt, const Address& addr) {
800 EmitLoadStore(SH, rt, addr); 809 EmitLoadStore(SH, rt, addr);
801 } 810 }
802 811
803 void sll(Register rd, Register rt, int sa) { 812 void sll(Register rd, Register rt, int sa) {
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1757 Register value, 1766 Register value,
1758 Label* no_update); 1767 Label* no_update);
1759 1768
1760 DISALLOW_ALLOCATION(); 1769 DISALLOW_ALLOCATION();
1761 DISALLOW_COPY_AND_ASSIGN(Assembler); 1770 DISALLOW_COPY_AND_ASSIGN(Assembler);
1762 }; 1771 };
1763 1772
1764 } // namespace dart 1773 } // namespace dart
1765 1774
1766 #endif // VM_ASSEMBLER_MIPS_H_ 1775 #endif // VM_ASSEMBLER_MIPS_H_
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