| Index: runtime/vm/constants_arm64.h
|
| diff --git a/runtime/vm/constants_arm64.h b/runtime/vm/constants_arm64.h
|
| index 913a69c89c41435860f4f3e4da49261cfeabf2ec..874b882f69b168f2a8bc6951d371c69c51fbf2c2 100644
|
| --- a/runtime/vm/constants_arm64.h
|
| +++ b/runtime/vm/constants_arm64.h
|
| @@ -364,6 +364,14 @@ enum LoadRegLiteralOp {
|
| LDRpc = LoadRegLiteralFixed,
|
| };
|
|
|
| +// C3.3.6
|
| +enum LoadStoreExclusiveOp {
|
| + LoadStoreExclusiveMask = 0x3f000000,
|
| + LoadStoreExclusiveFixed = B27,
|
| + LDXR = LoadStoreExclusiveFixed | B22,
|
| + STXR = LoadStoreExclusiveFixed,
|
| +};
|
| +
|
| // C3.3.7-10
|
| enum LoadStoreRegOp {
|
| LoadStoreRegMask = 0x3a000000,
|
| @@ -616,6 +624,7 @@ _V(UnconditionalBranchReg) \
|
| _V(LoadStoreReg) \
|
| _V(LoadStoreRegPair) \
|
| _V(LoadRegLiteral) \
|
| +_V(LoadStoreExclusive) \
|
| _V(AddSubImm) \
|
| _V(LogicalImm) \
|
| _V(MoveWide) \
|
| @@ -692,6 +701,8 @@ enum InstructionFields {
|
| kRtBits = 5,
|
| kRt2Shift = 10,
|
| kRt2Bits = 5,
|
| + kRsShift = 16,
|
| + kRsBits = 5,
|
|
|
| // V Registers.
|
| kVdShift = 0,
|
| @@ -892,6 +903,8 @@ class Instr {
|
| Bits(kRtShift, kRtBits)); }
|
| inline Register Rt2Field() const { return static_cast<Register>(
|
| Bits(kRt2Shift, kRt2Bits)); }
|
| + inline Register RsField() const { return static_cast<Register>(
|
| + Bits(kRsShift, kRsBits)); }
|
|
|
| inline VRegister VdField() const { return static_cast<VRegister>(
|
| Bits(kVdShift, kVdBits)); }
|
|
|