Enable concurrent sweep on MIPS and ARM64.

runtime/vm/assembler_mips.h

Index: runtime/vm/assembler_mips.h
diff --git a/runtime/vm/assembler_mips.h b/runtime/vm/assembler_mips.h
index 382d8339393e525595da77b3473bca7aa114bbde..c618d6a5368c99d1bb13aa600df034d4266bab30 100644
--- a/runtime/vm/assembler_mips.h
+++ b/runtime/vm/assembler_mips.h
@@ -663,6 +663,10 @@ class Assembler : public ValueObject {
     EmitLoadStore(LHU, rt, addr);
   }
 
+  void ll(Register rt, const Address& addr) {
+    EmitLoadStore(LL, rt, addr);
+  }
+
   void lui(Register rt, const Immediate& imm) {
     ASSERT(Utils::IsUint(kImmBits, imm.value()));
     const uint16_t imm_value = static_cast<uint16_t>(imm.value());
@@ -796,6 +800,11 @@ class Assembler : public ValueObject {
     EmitFpuLoadStore(SDC1, ft, addr);
   }
 
+  // rt = 1 on success, 0 on failure

[zra, 2016/02/25 04:02:35]

End comment with '.'

[rmacnak, 2016/02/25 23:31:46]

Done.

+  void sc(Register rt, const Address& addr) {
+    EmitLoadStore(SC, rt, addr);
+  }
+
   void sh(Register rt, const Address& addr) {
     EmitLoadStore(SH, rt, addr);
   }