Enable concurrent sweep on MIPS and ARM64.

runtime/vm/assembler_arm64.h

Index: runtime/vm/assembler_arm64.h
diff --git a/runtime/vm/assembler_arm64.h b/runtime/vm/assembler_arm64.h
index ffb6b768f42c28217fbb8d3351d800d2b678abe0..694be9c2b1729cbfbf727c45fc149d2d78238cde 100644
--- a/runtime/vm/assembler_arm64.h
+++ b/runtime/vm/assembler_arm64.h
@@ -757,6 +757,18 @@ class Assembler : public ValueObject {
     EmitLoadStoreRegPair(STP, rt, rt2, a, sz);
   }
 
+  void ldxr(Register rt, Register rn) {

[zra, 2016/02/25 04:02:35]

As on ARM, clrex looks like it would be useful to add as well, for testing.

[rmacnak, 2016/02/25 23:31:46]

Done.

+    // rt = value
+    // rn = address
+    EmitLoadStoreExclusive(LDXR, R31, rn, rt, kDoubleWord);
+  }
+  void stxr(Register rs, Register rt, Register rn) {
+    // rs = status (1 = failure, 0 = success)
+    // rt = value
+    // rn = address
+    EmitLoadStoreExclusive(STXR, rs, rn, rt, kDoubleWord);
+  }
+
   // Conditional select.
   void csel(Register rd, Register rn, Register rm, Condition cond) {
     EmitConditionalSelect(CSEL, rd, rn, rm, cond, kDoubleWord);
@@ -1714,6 +1726,24 @@ class Assembler : public ValueObject {
     Emit(encoding);
   }
 
+  void EmitLoadStoreExclusive(LoadStoreExclusiveOp op, Register rs, Register rn,
+                              Register rt, OperandSize sz = kDoubleWord) {
+    ASSERT(sz == kDoubleWord);
+    const int32_t size = B31 | B30;
+
+    ASSERT(rs != kNoRegister);
+    ASSERT(rn != kNoRegister);
+    ASSERT(rt != kNoRegister);
+
+    const int32_t encoding =
+        op | size |
+        (static_cast<int32_t>(rs) << kRsShift) |
+        (static_cast<int32_t>(rn) << kRnShift) |
+        (static_cast<int32_t>(rt) << kRtShift);
+
+    Emit(encoding);
+  }
+
   void EmitLoadStoreReg(LoadStoreRegOp op, Register rt, Address a,
                         OperandSize sz) {
     const Register crt = ConcreteRegister(rt);