| Index: test/CodeGen/JS/simd-shift.ll
|
| diff --git a/test/CodeGen/JS/simd-shift.ll b/test/CodeGen/JS/simd-shift.ll
|
| deleted file mode 100644
|
| index 7b4ab4d170c8571928d26309b66c063f4c70697b..0000000000000000000000000000000000000000
|
| --- a/test/CodeGen/JS/simd-shift.ll
|
| +++ /dev/null
|
| @@ -1,142 +0,0 @@
|
| -; RUN: llc < %s | FileCheck %s
|
| -
|
| -target datalayout = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-p:32:32:32-v128:32:128-n32-S128"
|
| -target triple = "asmjs-unknown-emscripten"
|
| -
|
| -; CHECK: function _test0($a) {
|
| -; CHECK: $a = SIMD_int32x4_check($a);
|
| -; CHECK: $shl = SIMD_int32x4_shiftLeftByScalar($a, 3);
|
| -; CHECK: return (SIMD_int32x4_check($shl));
|
| -; CHECK: }
|
| -define <4 x i32> @test0(<4 x i32> %a) {
|
| -entry:
|
| - %shl = shl <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>
|
| - ret <4 x i32> %shl
|
| -}
|
| -
|
| -; CHECK: function _test1($a,$b) {
|
| -; CHECK: $a = SIMD_int32x4_check($a);
|
| -; CHECK: $b = $b|0;
|
| -; CHECK: SIMD_int32x4_shiftLeftByScalar($a, $b);
|
| -; CHECK: return (SIMD_int32x4_check($shl));
|
| -; CHECK: }
|
| -define <4 x i32> @test1(<4 x i32> %a, i32 %b) {
|
| -entry:
|
| - %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0
|
| - %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
|
| - %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2
|
| - %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %b, i32 3
|
| - %shl = shl <4 x i32> %a, %vecinit3
|
| - ret <4 x i32> %shl
|
| -}
|
| -
|
| -; CHECK: function _test2($a,$b,$c) {
|
| -; CHECK: $a = SIMD_int32x4_check($a);
|
| -; CHECK: $b = $b|0;
|
| -; CHECK: $c = $c|0;
|
| -; CHECK: var $shl = SIMD_int32x4(0,0,0,0), $vecinit3 = SIMD_int32x4(0,0,0,0), label = 0, sp = 0;
|
| -; CHECK: $vecinit3 = SIMD_int32x4($b, $b, $c, $b);
|
| -; CHECK: $shl = SIMD_int32x4(($a.x|0) << ($vecinit3.x|0)|0, ($a.y|0) << ($vecinit3.y|0)|0, ($a.z|0) << ($vecinit3.z|0)|0, ($a.w|0) << ($vecinit3.w|0)|0);
|
| -; CHECK: return (SIMD_int32x4_check($shl));
|
| -; CHECK: }
|
| -define <4 x i32> @test2(<4 x i32> %a, i32 %b, i32 %c) {
|
| -entry:
|
| - %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0
|
| - %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
|
| - %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
|
| - %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %b, i32 3
|
| - %shl = shl <4 x i32> %a, %vecinit3
|
| - ret <4 x i32> %shl
|
| -}
|
| -
|
| -; CHECK: function _test3($a) {
|
| -; CHECK: $a = SIMD_int32x4_check($a);
|
| -; CHECK: SIMD_int32x4_shiftRightArithmeticByScalar($a, 3);
|
| -; CHECK: return (SIMD_int32x4_check($shr));
|
| -; CHECK: }
|
| -define <4 x i32> @test3(<4 x i32> %a) {
|
| -entry:
|
| - %shr = ashr <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>
|
| - ret <4 x i32> %shr
|
| -}
|
| -
|
| -; CHECK: function _test4($a,$b) {
|
| -; CHECK: $a = SIMD_int32x4_check($a);
|
| -; CHECK: $b = $b|0;
|
| -; CHECK: SIMD_int32x4_shiftRightArithmeticByScalar($a, $b);
|
| -; CHECK: return (SIMD_int32x4_check($shr));
|
| -; CHECK: }
|
| -define <4 x i32> @test4(<4 x i32> %a, i32 %b) {
|
| -entry:
|
| - %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0
|
| - %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
|
| - %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2
|
| - %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %b, i32 3
|
| - %shr = ashr <4 x i32> %a, %vecinit3
|
| - ret <4 x i32> %shr
|
| -}
|
| -
|
| -; CHECK: function _test5($a,$b,$c) {
|
| -; CHECK: $a = SIMD_int32x4_check($a);
|
| -; CHECK: $b = $b|0;
|
| -; CHECK: $c = $c|0;
|
| -; CHECK: var $shr = SIMD_int32x4(0,0,0,0), $vecinit3 = SIMD_int32x4(0,0,0,0), label = 0, sp = 0;
|
| -; CHECK: $vecinit3 = SIMD_int32x4($b, $c, $b, $b);
|
| -; CHECK: $shr = SIMD_int32x4(($a.x|0) >> ($vecinit3.x|0)|0, ($a.y|0) >> ($vecinit3.y|0)|0, ($a.z|0) >> ($vecinit3.z|0)|0, ($a.w|0) >> ($vecinit3.w|0)|0);
|
| -; CHECK: return (SIMD_int32x4_check($shr));
|
| -; CHECK: }
|
| -define <4 x i32> @test5(<4 x i32> %a, i32 %b, i32 %c) {
|
| -entry:
|
| - %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0
|
| - %vecinit1 = insertelement <4 x i32> %vecinit, i32 %c, i32 1
|
| - %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2
|
| - %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %b, i32 3
|
| - %shr = ashr <4 x i32> %a, %vecinit3
|
| - ret <4 x i32> %shr
|
| -}
|
| -
|
| -; CHECK: function _test6($a) {
|
| -; CHECK: $a = SIMD_int32x4_check($a);
|
| -; CHECK: SIMD_int32x4_shiftRightLogicalByScalar($a, 3);
|
| -; CHECK: return (SIMD_int32x4_check($lshr));
|
| -; CHECK: }
|
| -define <4 x i32> @test6(<4 x i32> %a) {
|
| -entry:
|
| - %lshr = lshr <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>
|
| - ret <4 x i32> %lshr
|
| -}
|
| -
|
| -; CHECK: function _test7($a,$b) {
|
| -; CHECK: $a = SIMD_int32x4_check($a);
|
| -; CHECK: $b = $b|0;
|
| -; CHECK: $lshr = SIMD_int32x4_shiftRightLogicalByScalar($a, $b);
|
| -; CHECK: return (SIMD_int32x4_check($lshr));
|
| -; CHECK: }
|
| -define <4 x i32> @test7(<4 x i32> %a, i32 %b) {
|
| -entry:
|
| - %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0
|
| - %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
|
| - %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2
|
| - %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %b, i32 3
|
| - %lshr = lshr <4 x i32> %a, %vecinit3
|
| - ret <4 x i32> %lshr
|
| -}
|
| -
|
| -; CHECK: function _test8($a,$b,$c) {
|
| -; CHECK: $a = SIMD_int32x4_check($a);
|
| -; CHECK: $b = $b|0;
|
| -; CHECK: $c = $c|0;
|
| -; CHECK: var $lshr = SIMD_int32x4(0,0,0,0), $vecinit3 = SIMD_int32x4(0,0,0,0), label = 0, sp = 0;
|
| -; CHECK: $vecinit3 = SIMD_int32x4($b, $b, $b, $c);
|
| -; CHECK: $lshr = SIMD_int32x4(($a.x|0) >>> ($vecinit3.x|0)|0, ($a.y|0) >>> ($vecinit3.y|0)|0, ($a.z|0) >>> ($vecinit3.z|0)|0, ($a.w|0) >>> ($vecinit3.w|0)|0);
|
| -; CHECK: return (SIMD_int32x4_check($lshr));
|
| -; CHECK: }
|
| -define <4 x i32> @test8(<4 x i32> %a, i32 %b, i32 %c) {
|
| -entry:
|
| - %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0
|
| - %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
|
| - %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2
|
| - %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %c, i32 3
|
| - %lshr = lshr <4 x i32> %a, %vecinit3
|
| - ret <4 x i32> %lshr
|
| -}
|
|
|