| OLD | NEW |
| (Empty) |
| 1 ; RUN: llc < %s | FileCheck %s | |
| 2 | |
| 3 target datalayout = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64
:64:64-p:32:32:32-v128:32:128-n32-S128" | |
| 4 target triple = "asmjs-unknown-emscripten" | |
| 5 | |
| 6 ; CHECK: function _test0($a) { | |
| 7 ; CHECK: $a = SIMD_int32x4_check($a); | |
| 8 ; CHECK: $shl = SIMD_int32x4_shiftLeftByScalar($a, 3); | |
| 9 ; CHECK: return (SIMD_int32x4_check($shl)); | |
| 10 ; CHECK: } | |
| 11 define <4 x i32> @test0(<4 x i32> %a) { | |
| 12 entry: | |
| 13 %shl = shl <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3> | |
| 14 ret <4 x i32> %shl | |
| 15 } | |
| 16 | |
| 17 ; CHECK: function _test1($a,$b) { | |
| 18 ; CHECK: $a = SIMD_int32x4_check($a); | |
| 19 ; CHECK: $b = $b|0; | |
| 20 ; CHECK: SIMD_int32x4_shiftLeftByScalar($a, $b); | |
| 21 ; CHECK: return (SIMD_int32x4_check($shl)); | |
| 22 ; CHECK: } | |
| 23 define <4 x i32> @test1(<4 x i32> %a, i32 %b) { | |
| 24 entry: | |
| 25 %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0 | |
| 26 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 | |
| 27 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2 | |
| 28 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %b, i32 3 | |
| 29 %shl = shl <4 x i32> %a, %vecinit3 | |
| 30 ret <4 x i32> %shl | |
| 31 } | |
| 32 | |
| 33 ; CHECK: function _test2($a,$b,$c) { | |
| 34 ; CHECK: $a = SIMD_int32x4_check($a); | |
| 35 ; CHECK: $b = $b|0; | |
| 36 ; CHECK: $c = $c|0; | |
| 37 ; CHECK: var $shl = SIMD_int32x4(0,0,0,0), $vecinit3 = SIMD_int32x4(0,0,0,0), l
abel = 0, sp = 0; | |
| 38 ; CHECK: $vecinit3 = SIMD_int32x4($b, $b, $c, $b); | |
| 39 ; CHECK: $shl = SIMD_int32x4(($a.x|0) << ($vecinit3.x|0)|0, ($a.y|0) << ($vecin
it3.y|0)|0, ($a.z|0) << ($vecinit3.z|0)|0, ($a.w|0) << ($vecinit3.w|0)|0); | |
| 40 ; CHECK: return (SIMD_int32x4_check($shl)); | |
| 41 ; CHECK: } | |
| 42 define <4 x i32> @test2(<4 x i32> %a, i32 %b, i32 %c) { | |
| 43 entry: | |
| 44 %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0 | |
| 45 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 | |
| 46 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 | |
| 47 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %b, i32 3 | |
| 48 %shl = shl <4 x i32> %a, %vecinit3 | |
| 49 ret <4 x i32> %shl | |
| 50 } | |
| 51 | |
| 52 ; CHECK: function _test3($a) { | |
| 53 ; CHECK: $a = SIMD_int32x4_check($a); | |
| 54 ; CHECK: SIMD_int32x4_shiftRightArithmeticByScalar($a, 3); | |
| 55 ; CHECK: return (SIMD_int32x4_check($shr)); | |
| 56 ; CHECK: } | |
| 57 define <4 x i32> @test3(<4 x i32> %a) { | |
| 58 entry: | |
| 59 %shr = ashr <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3> | |
| 60 ret <4 x i32> %shr | |
| 61 } | |
| 62 | |
| 63 ; CHECK: function _test4($a,$b) { | |
| 64 ; CHECK: $a = SIMD_int32x4_check($a); | |
| 65 ; CHECK: $b = $b|0; | |
| 66 ; CHECK: SIMD_int32x4_shiftRightArithmeticByScalar($a, $b); | |
| 67 ; CHECK: return (SIMD_int32x4_check($shr)); | |
| 68 ; CHECK: } | |
| 69 define <4 x i32> @test4(<4 x i32> %a, i32 %b) { | |
| 70 entry: | |
| 71 %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0 | |
| 72 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 | |
| 73 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2 | |
| 74 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %b, i32 3 | |
| 75 %shr = ashr <4 x i32> %a, %vecinit3 | |
| 76 ret <4 x i32> %shr | |
| 77 } | |
| 78 | |
| 79 ; CHECK: function _test5($a,$b,$c) { | |
| 80 ; CHECK: $a = SIMD_int32x4_check($a); | |
| 81 ; CHECK: $b = $b|0; | |
| 82 ; CHECK: $c = $c|0; | |
| 83 ; CHECK: var $shr = SIMD_int32x4(0,0,0,0), $vecinit3 = SIMD_int32x4(0,0,0,0), l
abel = 0, sp = 0; | |
| 84 ; CHECK: $vecinit3 = SIMD_int32x4($b, $c, $b, $b); | |
| 85 ; CHECK: $shr = SIMD_int32x4(($a.x|0) >> ($vecinit3.x|0)|0, ($a.y|0) >> ($vecin
it3.y|0)|0, ($a.z|0) >> ($vecinit3.z|0)|0, ($a.w|0) >> ($vecinit3.w|0)|0); | |
| 86 ; CHECK: return (SIMD_int32x4_check($shr)); | |
| 87 ; CHECK: } | |
| 88 define <4 x i32> @test5(<4 x i32> %a, i32 %b, i32 %c) { | |
| 89 entry: | |
| 90 %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0 | |
| 91 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %c, i32 1 | |
| 92 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2 | |
| 93 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %b, i32 3 | |
| 94 %shr = ashr <4 x i32> %a, %vecinit3 | |
| 95 ret <4 x i32> %shr | |
| 96 } | |
| 97 | |
| 98 ; CHECK: function _test6($a) { | |
| 99 ; CHECK: $a = SIMD_int32x4_check($a); | |
| 100 ; CHECK: SIMD_int32x4_shiftRightLogicalByScalar($a, 3); | |
| 101 ; CHECK: return (SIMD_int32x4_check($lshr)); | |
| 102 ; CHECK: } | |
| 103 define <4 x i32> @test6(<4 x i32> %a) { | |
| 104 entry: | |
| 105 %lshr = lshr <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3> | |
| 106 ret <4 x i32> %lshr | |
| 107 } | |
| 108 | |
| 109 ; CHECK: function _test7($a,$b) { | |
| 110 ; CHECK: $a = SIMD_int32x4_check($a); | |
| 111 ; CHECK: $b = $b|0; | |
| 112 ; CHECK: $lshr = SIMD_int32x4_shiftRightLogicalByScalar($a, $b); | |
| 113 ; CHECK: return (SIMD_int32x4_check($lshr)); | |
| 114 ; CHECK: } | |
| 115 define <4 x i32> @test7(<4 x i32> %a, i32 %b) { | |
| 116 entry: | |
| 117 %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0 | |
| 118 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 | |
| 119 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2 | |
| 120 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %b, i32 3 | |
| 121 %lshr = lshr <4 x i32> %a, %vecinit3 | |
| 122 ret <4 x i32> %lshr | |
| 123 } | |
| 124 | |
| 125 ; CHECK: function _test8($a,$b,$c) { | |
| 126 ; CHECK: $a = SIMD_int32x4_check($a); | |
| 127 ; CHECK: $b = $b|0; | |
| 128 ; CHECK: $c = $c|0; | |
| 129 ; CHECK: var $lshr = SIMD_int32x4(0,0,0,0), $vecinit3 = SIMD_int32x4(0,0,0,0),
label = 0, sp = 0; | |
| 130 ; CHECK: $vecinit3 = SIMD_int32x4($b, $b, $b, $c); | |
| 131 ; CHECK: $lshr = SIMD_int32x4(($a.x|0) >>> ($vecinit3.x|0)|0, ($a.y|0) >>> ($ve
cinit3.y|0)|0, ($a.z|0) >>> ($vecinit3.z|0)|0, ($a.w|0) >>> ($vecinit3.w|0)|0); | |
| 132 ; CHECK: return (SIMD_int32x4_check($lshr)); | |
| 133 ; CHECK: } | |
| 134 define <4 x i32> @test8(<4 x i32> %a, i32 %b, i32 %c) { | |
| 135 entry: | |
| 136 %vecinit = insertelement <4 x i32> undef, i32 %b, i32 0 | |
| 137 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 | |
| 138 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %b, i32 2 | |
| 139 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %c, i32 3 | |
| 140 %lshr = lshr <4 x i32> %a, %vecinit3 | |
| 141 ret <4 x i32> %lshr | |
| 142 } | |
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