Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceTargetLowering.cpp

Index: src/IceTargetLowering.cpp
diff --git a/src/IceTargetLowering.cpp b/src/IceTargetLowering.cpp
index d53fbab4e12a01d8179d97bbc3cce298e7ac7fc8..e1239fce3978d0d6fdc3ce7c55e48bc707f3d196 100644
--- a/src/IceTargetLowering.cpp
+++ b/src/IceTargetLowering.cpp
@@ -119,7 +119,7 @@ Variable *LoweringContext::availabilityGet(Operand *Src) const {
 namespace {
 
 void printRegisterSet(Ostream &Str, const llvm::SmallBitVector &Bitset,
-                      std::function<IceString(int32_t)> getRegName,
+                      std::function<IceString(RegNumT)> getRegName,
                       const IceString &LineIndentString) {
   constexpr size_t RegistersPerLine = 16;
   size_t Count = 0;
@@ -159,14 +159,14 @@ void splitToClassAndName(const IceString &RegName, IceString *SplitRegClass,
 void TargetLowering::filterTypeToRegisterSet(
     GlobalContext *Ctx, int32_t NumRegs,
     llvm::SmallBitVector TypeToRegisterSet[], size_t TypeToRegisterSetSize,
-    std::function<IceString(int32_t)> getRegName,
+    std::function<IceString(RegNumT)> getRegName,
     std::function<IceString(RegClass)> getRegClassName) {
   std::vector<llvm::SmallBitVector> UseSet(TypeToRegisterSetSize,
                                            llvm::SmallBitVector(NumRegs));
   std::vector<llvm::SmallBitVector> ExcludeSet(TypeToRegisterSetSize,
                                                llvm::SmallBitVector(NumRegs));
 
-  std::unordered_map<IceString, int32_t> RegNameToIndex;
+  std::unordered_map<IceString, RegNumT> RegNameToIndex;
   for (int32_t RegIndex = 0; RegIndex < NumRegs; ++RegIndex)
     RegNameToIndex[getRegName(RegIndex)] = RegIndex;