Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceTargetLoweringARM32.cpp

Index: src/IceTargetLoweringARM32.cpp
diff --git a/src/IceTargetLoweringARM32.cpp b/src/IceTargetLoweringARM32.cpp
index 4b70dadde7fccbb823684e6e2efab2c277dde208..dfb13df63222eeca8b483f71da4ddedab09bdb0b 100644
--- a/src/IceTargetLoweringARM32.cpp
+++ b/src/IceTargetLoweringARM32.cpp
@@ -346,7 +346,7 @@ void TargetARM32::staticInit(GlobalContext *Ctx) {
 
   filterTypeToRegisterSet(
       Ctx, RegARM32::Reg_NUM, TypeToRegisterSet,
-      llvm::array_lengthof(TypeToRegisterSet), [](int32_t RegNum) -> IceString {
+      llvm::array_lengthof(TypeToRegisterSet), [](RegNumT RegNum) -> IceString {
         // This function simply removes ", " from the register name.
         IceString Name = RegARM32::getRegName(RegNum);
         constexpr const char RegSeparator[] = ", ";
@@ -382,7 +382,7 @@ void copyRegAllocFromInfWeightVariable64On32(const VarList &Vars) {
     }
     Lo->setRegNum(FirstReg);
     Lo->setMustHaveReg();
-    Hi->setRegNum(FirstReg + 1);
+    Hi->setRegNum(RegNumT::fixme(FirstReg + 1));
     Hi->setMustHaveReg();
   }
 }
@@ -390,7 +390,7 @@ void copyRegAllocFromInfWeightVariable64On32(const VarList &Vars) {
 
 uint32_t TargetARM32::getCallStackArgumentsSizeBytes(const InstCall *Call) {
   TargetARM32::CallingConv CC;
-  int32_t DummyReg;
+  RegNumT DummyReg;
   size_t OutArgsSizeBytes = 0;
   for (SizeT i = 0, NumArgs = Call->getNumArgs(); i < NumArgs; ++i) {
     Operand *Arg = legalizeUndef(Call->getArg(i));
@@ -902,13 +902,12 @@ bool TargetARM32::doBranchOpt(Inst *I, const CfgNode *NextNode) {
   return false;
 }
 
-IceString TargetARM32::getRegName(SizeT RegNum, Type Ty) const {
-  assert(RegNum < RegARM32::Reg_NUM);
+IceString TargetARM32::getRegName(RegNumT RegNum, Type Ty) const {
   (void)Ty;
   return RegARM32::getRegName(RegNum);
 }
 
-Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
+Variable *TargetARM32::getPhysicalRegister(RegNumT RegNum, Type Ty) {
   static const Type DefaultType[] = {
 #define X(val, encode, name, cc_arg, scratch, preserved, stackptr, frameptr,   \
           isGPR, isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)       \
@@ -919,14 +918,14 @@ Variable *TargetARM32::getPhysicalRegister(SizeT RegNum, Type Ty) {
 #undef X
   };
 
-  assert(RegNum < RegARM32::Reg_NUM);
+  assert(unsigned(RegNum) < RegARM32::Reg_NUM);
   if (Ty == IceType_void) {
-    assert(RegNum < llvm::array_lengthof(DefaultType));
+    assert(unsigned(RegNum) < llvm::array_lengthof(DefaultType));
     Ty = DefaultType[RegNum];
   }
   if (PhysicalRegisters[Ty].empty())
     PhysicalRegisters[Ty].resize(RegARM32::Reg_NUM);
-  assert(RegNum < PhysicalRegisters[Ty].size());
+  assert(unsigned(RegNum) < PhysicalRegisters[Ty].size());
   Variable *Reg = PhysicalRegisters[Ty][RegNum];
   if (Reg == nullptr) {
     Reg = Func->makeVariable(Ty);
@@ -963,8 +962,8 @@ void TargetARM32::emitVariable(const Variable *Var) const {
   }
   assert(!Var->isRematerializable());
   int32_t Offset = Var->getStackOffset();
-  int32_t BaseRegNum = Var->getBaseRegNum();
-  if (BaseRegNum == Variable::NoRegister) {
+  RegNumT BaseRegNum = Var->getBaseRegNum();
+  if (BaseRegNum == RegNumT::NoRegister) {
     BaseRegNum = getFrameOrStackReg();
   }
   const Type VarTy = Var->getType();
@@ -984,7 +983,7 @@ TargetARM32::CallingConv::CallingConv()
       FP64Args(FP64ArgInitializer.rbegin(), FP64ArgInitializer.rend()),
       Vec128Args(Vec128ArgInitializer.rbegin(), Vec128ArgInitializer.rend()) {}
 
-bool TargetARM32::CallingConv::argInGPR(Type Ty, int32_t *Reg) {
+bool TargetARM32::CallingConv::argInGPR(Type Ty, RegNumT *Reg) {
   CfgVector<SizeT> *Source;
 
   switch (Ty) {
@@ -1026,7 +1025,7 @@ void TargetARM32::CallingConv::discardUnavailableGPRsAndTheirAliases(
   }
 }
 
-bool TargetARM32::CallingConv::argInVFP(Type Ty, int32_t *Reg) {
+bool TargetARM32::CallingConv::argInVFP(Type Ty, RegNumT *Reg) {
   CfgVector<SizeT> *Source;
 
   switch (Ty) {
@@ -1076,7 +1075,7 @@ void TargetARM32::lowerArguments() {
   for (SizeT I = 0, E = Args.size(); I < E; ++I) {
     Variable *Arg = Args[I];
     Type Ty = Arg->getType();
-    int RegNum;
+    RegNumT RegNum;
     if (isScalarIntegerType(Ty)) {
       if (!CC.argInGPR(Ty, &RegNum)) {
         continue;
@@ -1362,7 +1361,7 @@ void TargetARM32::addProlog(CfgNode *Node) {
   size_t InArgsSizeBytes = 0;
   TargetARM32::CallingConv CC;
   for (Variable *Arg : Args) {
-    int32_t DummyReg;
+    RegNumT DummyReg;
     const Type Ty = Arg->getType();
 
     // Skip arguments passed in registers.
@@ -1481,7 +1480,7 @@ bool TargetARM32::isLegalMemOffset(Type Ty, int32_t Offset) const {
 }
 
 Variable *TargetARM32::PostLoweringLegalizer::newBaseRegister(
-    Variable *Base, int32_t Offset, int32_t ScratchRegNum) {
+    Variable *Base, int32_t Offset, RegNumT ScratchRegNum) {
   // Legalize will likely need a movw/movt combination, but if the top bits are
   // all 0 from negating the offset and subtracting, we could use that instead.
   const bool ShouldSub = Offset != 0 && (-Offset & 0xFFFF0000) == 0;
@@ -1500,7 +1499,7 @@ Variable *TargetARM32::PostLoweringLegalizer::newBaseRegister(
 
   if (ScratchRegNum == Target->getReservedTmpReg()) {
     const bool BaseIsStackOrFramePtr =
-        Base->getRegNum() == static_cast<int32_t>(Target->getFrameOrStackReg());
+        Base->getRegNum() == Target->getFrameOrStackReg();
     // There is currently no code path that would trigger this assertion, so we
     // leave this assertion here in case it is ever violated. This is not a
     // fatal error (thus the use of assert() and not llvm::report_fatal_error)
@@ -1607,10 +1606,9 @@ void TargetARM32::PostLoweringLegalizer::legalizeMov(InstARM32Mov *MovInstr) {
 
       // ExtraOffset is only needed for frame-pointer based frames as we have
       // to account for spill storage.
-      const int32_t ExtraOffset =
-          (static_cast<SizeT>(Var->getRegNum()) == Target->getFrameReg())
-              ? Target->getFrameFixedAllocaOffset()
-              : 0;
+      const int32_t ExtraOffset = (Var->getRegNum() == Target->getFrameReg())
+                                      ? Target->getFrameFixedAllocaOffset()
+                                      : 0;
 
       const int32_t Offset = Var->getStackOffset() + ExtraOffset;
       Variable *Base = Target->getPhysicalRegister(Var->getRegNum());
@@ -1678,10 +1676,9 @@ TargetARM32::PostLoweringLegalizer::legalizeMemOperand(OperandARM32Mem *Mem,
   Variable *Base = Mem->getBase();
   int32_t Offset = Mem->isRegReg() ? 0 : Mem->getOffset()->getValue();
   if (Base->isRematerializable()) {
-    const int32_t ExtraOffset =
-        (static_cast<SizeT>(Base->getRegNum()) == Target->getFrameReg())
-            ? Target->getFrameFixedAllocaOffset()
-            : 0;
+    const int32_t ExtraOffset = (Base->getRegNum() == Target->getFrameReg())
+                                    ? Target->getFrameFixedAllocaOffset()
+                                    : 0;
     Offset += Base->getStackOffset() + ExtraOffset;
     Base = Target->getPhysicalRegister(Base->getRegNum());
     assert(!Base->isRematerializable());
@@ -1901,7 +1898,7 @@ llvm::SmallBitVector TargetARM32::getRegisterSet(RegSetMask Include,
                                                  RegSetMask Exclude) const {
   llvm::SmallBitVector Registers(RegARM32::Reg_NUM);
 
-  for (int32_t i = 0; i < RegARM32::Reg_NUM; ++i) {
+  for (uint32_t i = 0; i < RegARM32::Reg_NUM; ++i) {

[Eric Holk, 2016/02/08 19:37:10]

Would something like a Register iterator make sense, so that we could do
something like `for(RegNumT i : RegARM32::AllRegisters)`?

It's probably more code than it's worth for just this one instance...

[Jim Stichnoth, 2016/02/09 19:33:39]

Good idea for future work. :)

I had thought about making AllRegisters a subclass of RegNumT and then this kind
of iteration would fit right in, but John is concerned about upcast/downcast
issues.

But along those lines, I was thinking of wrapping llvm::SmallBitVector so that
find_first() and find_next() could directly return usable RegNumT values...

[Eric Holk, 2016/02/10 01:11:30]

Cool :)

     const auto &Entry = RegARM32::RegTable[i];
     if (Entry.Scratch && (Include & RegSet_CallerSave))
       Registers[i] = true;
@@ -3361,8 +3358,8 @@ void TargetARM32::lowerCall(const InstCall *Instr) {
   // Assign arguments to registers and stack. Also reserve stack.
   TargetARM32::CallingConv CC;
   // Pair of Arg Operand -> GPR number assignments.
-  llvm::SmallVector<std::pair<Operand *, int32_t>, NumGPRArgs> GPRArgs;
-  llvm::SmallVector<std::pair<Operand *, int32_t>, NumFP32Args> FPArgs;
+  llvm::SmallVector<std::pair<Operand *, RegNumT>, NumGPRArgs> GPRArgs;
+  llvm::SmallVector<std::pair<Operand *, RegNumT>, NumFP32Args> FPArgs;
   // Pair of Arg Operand -> stack offset.
   llvm::SmallVector<std::pair<Operand *, int32_t>, 8> StackArgs;
   size_t ParameterAreaSizeBytes = 0;
@@ -3373,7 +3370,7 @@ void TargetARM32::lowerCall(const InstCall *Instr) {
     Operand *Arg = legalizeUndef(Instr->getArg(i));
     const Type Ty = Arg->getType();
     bool InReg = false;
-    int32_t Reg;
+    RegNumT Reg;
     if (isScalarIntegerType(Ty)) {
       InReg = CC.argInGPR(Ty, &Reg);
     } else {
@@ -5457,7 +5454,7 @@ void TargetARM32::prelowerPhis() {
   PhiLowering::prelowerPhis32Bit<TargetARM32>(this, Context.getNode(), Func);
 }
 
-Variable *TargetARM32::makeVectorOfZeros(Type Ty, int32_t RegNum) {
+Variable *TargetARM32::makeVectorOfZeros(Type Ty, RegNumT RegNum) {
   Variable *Reg = makeReg(Ty, RegNum);
   Context.insert<InstFakeDef>(Reg);
   UnimplementedError(Func->getContext()->getFlags());
@@ -5466,7 +5463,7 @@ Variable *TargetARM32::makeVectorOfZeros(Type Ty, int32_t RegNum) {
 
 // Helper for legalize() to emit the right code to lower an operand to a
 // register of the appropriate type.
-Variable *TargetARM32::copyToReg(Operand *Src, int32_t RegNum) {
+Variable *TargetARM32::copyToReg(Operand *Src, RegNumT RegNum) {
   Type Ty = Src->getType();
   Variable *Reg = makeReg(Ty, RegNum);
   if (auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Src)) {
@@ -5479,7 +5476,7 @@ Variable *TargetARM32::copyToReg(Operand *Src, int32_t RegNum) {
 
 // TODO(jpp): remove unneeded else clauses in legalize.
 Operand *TargetARM32::legalize(Operand *From, LegalMask Allowed,
-                               int32_t RegNum) {
+                               RegNumT RegNum) {
   Type Ty = From->getType();
   // Assert that a physical register is allowed. To date, all calls to
   // legalize() allow a physical register. Legal_Flex converts registers to the
@@ -5487,7 +5484,7 @@ Operand *TargetARM32::legalize(Operand *From, LegalMask Allowed,
   assert(Allowed & Legal_Reg);
 
   // Copied ipsis literis from TargetX86Base<Machine>.
-  if (RegNum == Variable::NoRegister) {
+  if (RegNum == RegNumT::NoRegister) {
     if (Variable *Subst = getContext().availabilityGet(From)) {
       // At this point we know there is a potential substitution available.
       if (!Subst->isRematerializable() && Subst->mustHaveReg() &&
@@ -5671,7 +5668,7 @@ Operand *TargetARM32::legalize(Operand *From, LegalMask Allowed,
     //   register, or
     //   RegNum is required and Var->getRegNum() doesn't match.
     if ((!(Allowed & Legal_Mem) && !MustHaveRegister) ||
-        (RegNum != Variable::NoRegister && RegNum != Var->getRegNum())) {
+        (RegNum != RegNumT::NoRegister && RegNum != Var->getRegNum())) {
       From = copyToReg(From, RegNum);
     }
     return From;
@@ -5682,12 +5679,12 @@ Operand *TargetARM32::legalize(Operand *From, LegalMask Allowed,
 }
 
 /// Provide a trivial wrapper to legalize() for this common usage.
-Variable *TargetARM32::legalizeToReg(Operand *From, int32_t RegNum) {
+Variable *TargetARM32::legalizeToReg(Operand *From, RegNumT RegNum) {
   return llvm::cast<Variable>(legalize(From, Legal_Reg, RegNum));
 }
 
 /// Legalize undef values to concrete values.
-Operand *TargetARM32::legalizeUndef(Operand *From, int32_t RegNum) {
+Operand *TargetARM32::legalizeUndef(Operand *From, RegNumT RegNum) {
   Type Ty = From->getType();
   if (llvm::isa<ConstantUndef>(From)) {
     // Lower undefs to zero. Another option is to lower undefs to an
@@ -5735,12 +5732,12 @@ Variable64On32 *TargetARM32::makeI64RegPair() {
   return Reg;
 }
 
-Variable *TargetARM32::makeReg(Type Type, int32_t RegNum) {
+Variable *TargetARM32::makeReg(Type Type, RegNumT RegNum) {
   // There aren't any 64-bit integer registers for ARM32.
   assert(Type != IceType_i64);
-  assert(AllowTemporaryWithNoReg || RegNum != Variable::NoRegister);
+  assert(AllowTemporaryWithNoReg || RegNum != RegNumT::NoRegister);
   Variable *Reg = Func->makeVariable(Type);
-  if (RegNum == Variable::NoRegister)
+  if (RegNum == RegNumT::NoRegister)
     Reg->setMustHaveReg();
   else
     Reg->setRegNum(RegNum);
@@ -5748,7 +5745,7 @@ Variable *TargetARM32::makeReg(Type Type, int32_t RegNum) {
 }
 
 void TargetARM32::alignRegisterPow2(Variable *Reg, uint32_t Align,
-                                    int32_t TmpRegNum) {
+                                    RegNumT TmpRegNum) {
   assert(llvm::isPowerOf2_32(Align));
   uint32_t RotateAmt;
   uint32_t Immed_8;
@@ -5775,7 +5772,7 @@ void TargetARM32::postLower() {
 }
 
 void TargetARM32::makeRandomRegisterPermutation(
-    llvm::SmallVectorImpl<int32_t> &Permutation,
+    llvm::SmallVectorImpl<RegNumT> &Permutation,
     const llvm::SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   (void)Permutation;
   (void)ExcludeRegisters;