Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 89854b18a60fdaf6cb66f1c2f6f7462214da4b71..1f12751623724cffd64923efaa1395b01ba40226 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -195,7 +195,7 @@ RegARM32::GPRRegister getGPRReg(IValueT Shift, IValueT Value) {
 
 IValueT getEncodedGPRegNum(const Variable *Var) {
   assert(Var->hasReg());
-  int32_t Reg = Var->getRegNum();
+  RegNumT Reg = Var->getRegNum();
   return llvm::isa<Variable64On32>(Var) ? RegARM32::getI64PairFirstGPRNum(Reg)
                                         : RegARM32::getEncodedGPR(Reg);
 }

[Eric Holk, 2016/02/08 19:37:09]

Optional, but would it make sense to turn getI64PairFirstGPRNum and
getEncodedGPR into member functions of something like RegNumARM32T?

[Jim Stichnoth, 2016/02/09 19:33:39]

Those functions are supposed to be GPRRegister which are encoded register
values.  I think that's already the right representation.  However, maybe this
function should be returning GPRRegister instead of IValueT, but that's probably
beyond the scope of this CL.

[Karl, 2016/02/09 21:52:14]

Be careful when removing IValueT. It was explicitly defined to guarantee that we
can bit-union in bits of an ARM instruction.

[Eric Holk, 2016/02/10 01:11:30]

Sounds good.

@@ -470,8 +470,8 @@ EncodedOperand encodeAddress(const Operand *Opnd, IValueT &Value,
     IOffsetT Offset = Var->getStackOffset();
     if (!Utils::IsAbsoluteUint(12, Offset))
       return CantEncode;
-    int32_t BaseRegNum = Var->getBaseRegNum();
-    if (BaseRegNum == Variable::NoRegister)
+    RegNumT BaseRegNum = Var->getBaseRegNum();
+    if (BaseRegNum == RegNumT::NoRegister)
       BaseRegNum = TInfo.FrameOrStackReg;
     Value = encodeImmRegOffset(ImmEncoding, BaseRegNum, Offset,
                                OperandARM32Mem::Offset);