Subzero: Use a proper RegNumT type instead of int32_t/SizeT.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 177 matching lines @@
 // Extract out a Bit in Value.
 bool isBitSet(IValueT Bit, IValueT Value) { return (Value & Bit) == Bit; }
 
 // Returns the GPR register at given Shift in Value.
 RegARM32::GPRRegister getGPRReg(IValueT Shift, IValueT Value) {
   return decodeGPRRegister((Value >> Shift) & 0xF);
 }
 
 IValueT getEncodedGPRegNum(const Variable *Var) {
   assert(Var->hasReg());
-  int32_t Reg = Var->getRegNum();
+  RegNumT Reg = Var->getRegNum();
   return llvm::isa<Variable64On32>(Var) ? RegARM32::getI64PairFirstGPRNum(Reg)
                                         : RegARM32::getEncodedGPR(Reg);
 }

[Eric Holk, 2016/02/08 19:37:09]

Optional, but would it make sense to turn getI64PairFirstGPRNum and
getEncodedGPR into member functions of something like RegNumARM32T?

[Jim Stichnoth, 2016/02/09 19:33:39]

Those functions are supposed to be GPRRegister which are encoded register
values.  I think that's already the right representation.  However, maybe this
function should be returning GPRRegister instead of IValueT, but that's probably
beyond the scope of this CL.

[Karl, 2016/02/09 21:52:14]

Be careful when removing IValueT. It was explicitly defined to guarantee that we
can bit-union in bits of an ARM instruction.

[Eric Holk, 2016/02/10 01:11:30]

Sounds good.

 
 IValueT getEncodedSRegNum(const Variable *Var) {
   assert(Var->hasReg());
   return RegARM32::getEncodedSReg(Var->getRegNum());
 }
 
 IValueT getEncodedDRegNum(const Variable *Var) {
   return RegARM32::getEncodedDReg(Var->getRegNum());
 }
 
@@ skipping 251 matching lines @@
                              const AssemblerARM32::TargetInfo &TInfo,
                              EncodedImmAddress ImmEncoding) {
   Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     // Should be a stack variable, with an offset.
     if (Var->hasReg())
       return CantEncode;
     IOffsetT Offset = Var->getStackOffset();
     if (!Utils::IsAbsoluteUint(12, Offset))
       return CantEncode;
-    int32_t BaseRegNum = Var->getBaseRegNum();
-    if (BaseRegNum == Variable::NoRegister)
+    RegNumT BaseRegNum = Var->getBaseRegNum();
+    if (BaseRegNum == RegNumT::NoRegister)
       BaseRegNum = TInfo.FrameOrStackReg;
     Value = encodeImmRegOffset(ImmEncoding, BaseRegNum, Offset,
                                OperandARM32Mem::Offset);
     return EncodedAsImmRegOffset;
   }
   if (const auto *Mem = llvm::dyn_cast<OperandARM32Mem>(Opnd)) {
     Variable *Var = Mem->getBase();
     if (!Var->hasReg())
       return CantEncode;
     IValueT Rn = getEncodedGPRegNum(Var);
@@ skipping 2566 matching lines @@
   constexpr const char *Vsqrts = "vsqrts";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vsqrts);
   IValueT Sm = encodeSRegister(OpSm, "Sm", Vsqrts);
   constexpr IValueT VsqrtsOpcode = B23 | B21 | B20 | B16 | B7 | B6;
   constexpr IValueT S0 = 0;
   emitVFPsss(Cond, VsqrtsOpcode, Sd, S0, Sm);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice