Add the trap instruction to the integrated ARM assembler.

tests_lit/assembler/arm32/trap.ll

Index: tests_lit/assembler/arm32/trap.ll
diff --git a/tests_lit/assembler/arm32/vmrs.ll b/tests_lit/assembler/arm32/trap.ll
similarity index 59%
copy from tests_lit/assembler/arm32/vmrs.ll
copy to tests_lit/assembler/arm32/trap.ll
index f635389bf9ffbe9c226c090f9dd8cb392ddbbee8..5246e527ef689565be7fda485c7c1a7e87277d64 100644
--- a/tests_lit/assembler/arm32/vmrs.ll
+++ b/tests_lit/assembler/arm32/trap.ll
@@ -1,4 +1,7 @@
-; Test the "vmrs APSR_nzcv, FPSCR" form of the VMRS instruction.
+; Show that we can translate IR instruction "trap".
+
+; Note: We use integer division to test this, since a trap is inserted

[Jim Stichnoth, 2016/01/29 20:49:53]

Could you also test the "unreachable" bitcode instruction?

[Karl, 2016/01/29 22:00:36]

Done.

+; if one divides by zero.
 
 ; REQUIRES: allow_dump
 
@@ -20,19 +23,20 @@
 ; RUN:   --args -Om1 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
-define internal i32 @testVmrsASPR_nzcv() {
-; ASM-LABEL: testVmrsASPR_nzcv:
-; DIS-LABEL: 00000000 <testVmrsASPR_nzcv>:
+define internal i32 @testTrap(i32 %v1, i32 %v2) {
+; ASM-LABEL: testTrap:
+; DIS-LABEL: 00000000 <testTrap>:
+; IASM-LABEL: testTrap:
 
-entry:
-; ASM: .LtestVmrsASPR_nzcv$entry:
+  %res = udiv i32 %v1, %v2
 
-  %test = fcmp olt float 0.0, 0.0
+; ASM:          bne
+; DIS:        18:	1a000000

[Jim Stichnoth, 2016/01/29 20:49:53]

tabs

+; IASM-NOT:     bne
 
-; ASM:  vmrs    APSR_nzcv, FPSCR
-; DIS:   14:    eef1fa10
-; IASM-NOT: vmrs
+; ASM-NEXT:     .long 0xe7fedef0
+; DIS-NEXT:   1c:	e7fedef0
+; IASM-NOT:     .long
 
-  %result = zext i1 %test to i32
-  ret i32 %result
+  ret i32 %res
 }