Detect cache line size on Linux for PPC hosts.

src/arm64/cpu-arm64.cc

Index: src/arm64/cpu-arm64.cc
diff --git a/src/arm64/cpu-arm64.cc b/src/arm64/cpu-arm64.cc
index cf2cc572155ac43a7ca5438a2afed43458a89e18..888528346fcc129b11e421c068b04fb93fade575 100644
--- a/src/arm64/cpu-arm64.cc
+++ b/src/arm64/cpu-arm64.cc
@@ -12,32 +12,6 @@
 namespace v8 {
 namespace internal {
 
-class CacheLineSizes {
- public:
-  CacheLineSizes() {
-#ifdef USE_SIMULATOR
-    cache_type_register_ = 0;
-#else
-    // Copy the content of the cache type register to a core register.
-    __asm__ __volatile__ ("mrs %[ctr], ctr_el0"  // NOLINT
-                          : [ctr] "=r" (cache_type_register_));
-#endif
-  }
-
-  uint32_t icache_line_size() const { return ExtractCacheLineSize(0); }
-  uint32_t dcache_line_size() const { return ExtractCacheLineSize(16); }
-
- private:
-  uint32_t ExtractCacheLineSize(int cache_line_size_shift) const {
-    // The cache type register holds the size of cache lines in words as a
-    // power of two.
-    return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xf);
-  }
-
-  uint32_t cache_type_register_;
-};
-
-
 void CpuFeatures::FlushICache(void* address, size_t length) {
 #ifdef V8_HOST_ARCH_ARM64
   // The code below assumes user space cache operations are allowed. The goal
@@ -46,9 +20,8 @@ void CpuFeatures::FlushICache(void* address, size_t length) {
 
   uintptr_t start = reinterpret_cast<uintptr_t>(address);
   // Sizes will be used to generate a mask big enough to cover a pointer.
-  CacheLineSizes sizes;
-  uintptr_t dsize = sizes.dcache_line_size();
-  uintptr_t isize = sizes.icache_line_size();
+  uintptr_t dsize = CpuFeatures::dcache_line_size();
+  uintptr_t isize = CpuFeatures::icache_line_size();
   // Cache line sizes are always a power of 2.
   DCHECK(CountSetBits(dsize, 64) == 1);
   DCHECK(CountSetBits(isize, 64) == 1);