Detect cache line size on Linux for PPC hosts.

src/arm64/cpu-arm64.cc

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 // CPU specific code for arm independent of OS goes here.
 
 #if V8_TARGET_ARCH_ARM64
 
 #include "src/arm64/utils-arm64.h"
 #include "src/assembler.h"
 
 namespace v8 {
 namespace internal {
 
-class CacheLineSizes {
- public:
-  CacheLineSizes() {
-#ifdef USE_SIMULATOR
-    cache_type_register_ = 0;
-#else
-    // Copy the content of the cache type register to a core register.
-    __asm__ __volatile__ ("mrs %[ctr], ctr_el0"  // NOLINT
-                          : [ctr] "=r" (cache_type_register_));
-#endif
-  }
-
-  uint32_t icache_line_size() const { return ExtractCacheLineSize(0); }
-  uint32_t dcache_line_size() const { return ExtractCacheLineSize(16); }
-
- private:
-  uint32_t ExtractCacheLineSize(int cache_line_size_shift) const {
-    // The cache type register holds the size of cache lines in words as a
-    // power of two.
-    return 4 << ((cache_type_register_ >> cache_line_size_shift) & 0xf);
-  }
-
-  uint32_t cache_type_register_;
-};
-
-
 void CpuFeatures::FlushICache(void* address, size_t length) {
 #ifdef V8_HOST_ARCH_ARM64
   // The code below assumes user space cache operations are allowed. The goal
   // of this routine is to make sure the code generated is visible to the I
   // side of the CPU.
 
   uintptr_t start = reinterpret_cast<uintptr_t>(address);
   // Sizes will be used to generate a mask big enough to cover a pointer.
-  CacheLineSizes sizes;
-  uintptr_t dsize = sizes.dcache_line_size();
-  uintptr_t isize = sizes.icache_line_size();
+  uintptr_t dsize = CpuFeatures::dcache_line_size();
+  uintptr_t isize = CpuFeatures::icache_line_size();
   // Cache line sizes are always a power of 2.
   DCHECK(CountSetBits(dsize, 64) == 1);
   DCHECK(CountSetBits(isize, 64) == 1);
   uintptr_t dstart = start & ~(dsize - 1);
   uintptr_t istart = start & ~(isize - 1);
   uintptr_t end = start + length;
 
   __asm__ __volatile__ (  // NOLINT
     // Clean every line of the D cache containing the target data.
     "0:                                \n\t"
@@ skipping 44 matching lines @@
     // move this code before the code is generated.
     : "cc", "memory"
   );  // NOLINT
 #endif  // V8_HOST_ARCH_ARM64
 }
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_TARGET_ARCH_ARM64