Subzero: Mips: Lower some i64 arithmetic instructions

tests_lit/llvm2ice_tests/64bit.pnacl.ll

Index: tests_lit/llvm2ice_tests/64bit.pnacl.ll
diff --git a/tests_lit/llvm2ice_tests/64bit.pnacl.ll b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
index 241c4ecc526fdfa828d20f81906c4524787d68e6..24bf86ca7b04ec7ef335f5b3d64d536568de5f8b 100644
--- a/tests_lit/llvm2ice_tests/64bit.pnacl.ll
+++ b/tests_lit/llvm2ice_tests/64bit.pnacl.ll
@@ -26,6 +26,16 @@
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix ARM32 --check-prefix ARM32-OM1 %s
 
+; TODO(rkotler): Stop skipping unimplemented parts (via --skip-unimplemented)
+; once enough infrastructure is in. Also, switch to --filetype=obj
+; when possible.
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command %p2i --filetype=asm --assemble \
+; RUN:   --disassemble --target mips32 -i %s --args  -O2 --skip-unimplemented \
+; RUN:   -allow-externally-defined-symbols \
+; RUN:   | %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command FileCheck --check-prefix MIPS32 --check-prefix MIPS32-O2 %s

[Jim Stichnoth, 2016/01/30 17:03:29]

TIL that FileCheck can take multiple --check-prefix arguments.  I wish I had
known about this before!

Three problems, though:

1. None of the check lines below use MIPS32-O2.

2. Many of the check lines below use MIPS which is not part of any RUN command.

3. You really need another RUN command that tests -Om1.

[rkotlerimgtec, 2016/01/30 23:48:31]

This just mimicks what ARM is doing here. -Om1 was not in the ARM
patch that this follows. There are some things regarding the stack that need to
be there that had not been implemented at this stage of ARM development.

[Jim Stichnoth, 2016/01/31 05:29:47]

All the same, using -Om1 exposes lowering/legalization problems (operands that
should be in registers but aren't) and this is an ideal setting to find and fix
them.

Spoiler alert: if you change it to -Om1 here and make all the other changes I
suggested, you will get a passing test. :)

+
 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
@@ -36,6 +46,9 @@ entry:
   ret i32 %b
 }
 
+; MIPS32-LABEL: ignore64BitArg
+; MIPS: move v0,a2
+
 define internal i32 @pass64BitArg(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f) {
 entry:
   %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 %b)
@@ -102,6 +115,8 @@ entry:
 ; ARM32:      mov     r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 
+; MIPS32-LABEL: pass64BitArg
+
 
 declare i32 @ignore64BitArgNoInline(i64, i32, i64)
 
@@ -167,6 +182,9 @@ entry:
 ; ARM32: mov {{.*}}, #123
 ; ARM32: bl {{.*}} ignore64BitArgNoInline
 
+; MIPS32-LABEL: pass64BitUndefArg
+; MIPS: jr  ra
+
 define internal i64 @return64BitArg(i64 %padding, i64 %a) {
 entry:
   ret i64 %a
@@ -184,6 +202,11 @@ entry:
 ; ARM32: mov {{.*}}, r3
 ; ARM32: bx lr
 
+; MIPS-LABEL; return64BitArg
+; MIPS: move v0,a2
+; MIPS: move v1,a3
+; MIPS: jr ra
+
 define internal i64 @return64BitConst() {
 entry:
   ret i64 -2401053092306725256
@@ -202,6 +225,13 @@ entry:
 ; ARM32: movw r1, #48879 ; 0xbeef
 ; ARM32: movt r1, #57005 ; 0xdead
 
+; MIPS32-LABEL: return64BitConst
+; MIPS32: lui v0,0x1234
+; MIPS32: ori v0,v0,0x5678
+; MIPS32: lui v1,0xdead
+; MIPS32: ori v1,v1,0xbeef
+; MIPS32: jr ra
+
 define internal i64 @add64BitSigned(i64 %a, i64 %b) {
 entry:
   %add = add i64 %b, %a
@@ -219,6 +249,12 @@ entry:
 ; ARM32: adds
 ; ARM32: adc
 
+; MIPS-LABEL: add64BitSigned
+; MIPS: addu
+; MIPS: sltu
+; MIPS: addu
+; MIPS: addu
+
 define internal i64 @add64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %add = add i64 %b, %a
@@ -236,6 +272,12 @@ entry:
 ; ARM32: adds
 ; ARM32: adc
 
+; MIPS-LABEL: add64BitUnsigned
+; MIPS: addu
+; MIPS: sltu
+; MIPS: addu
+; MIPS: addu
+
 define internal i64 @sub64BitSigned(i64 %a, i64 %b) {
 entry:
   %sub = sub i64 %a, %b
@@ -253,6 +295,12 @@ entry:
 ; ARM32: subs
 ; ARM32: sbc
 
+; MIPS-LABEL: sub64BitSigned
+; MIPS: subu
+; MIPS: sltu
+; MIPS: addu
+; MIPS: subu
+
 define internal i64 @sub64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %sub = sub i64 %a, %b
@@ -270,6 +318,12 @@ entry:
 ; ARM32: subs
 ; ARM32: sbc
 
+; MIPS-LABEL: sub64BitUnsigned
+; MIPS: subu
+; MIPS: sltu
+; MIPS: addu
+; MIPS: subu
+
 define internal i64 @mul64BitSigned(i64 %a, i64 %b) {
 entry:
   %mul = mul i64 %b, %a
@@ -604,6 +658,10 @@ entry:
 ; ARM32: and
 ; ARM32: and
 
+; MIPS32-LABEL: and64BitSigned
+; MIPS32: and
+; MIPS32: and
+
 define internal i64 @and64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %and = and i64 %b, %a
@@ -621,6 +679,10 @@ entry:
 ; ARM32: and
 ; ARM32: and
 
+; MIPS32-LABEL: and64BitUnsigned
+; MIPS32: and
+; MIPS32: and
+
 define internal i64 @or64BitSigned(i64 %a, i64 %b) {
 entry:
   %or = or i64 %b, %a
@@ -638,6 +700,11 @@ entry:
 ; ARM32: orr
 ; ARM32: orr
 
+; MIPS32-LABEL: or64BitSigned
+; MIPS32: or
+; MIPS32: or
+
+

[Jim Stichnoth, 2016/01/30 17:03:29]

This and the next two tests add 2 blank lines instead of 1...

[rkotlerimgtec, 2016/01/30 23:48:31]

Done.

 define internal i64 @or64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %or = or i64 %b, %a
@@ -655,6 +722,11 @@ entry:
 ; ARM32: orr
 ; ARM32: orr
 
+; MIPS32-LABEL: or64BitUnsigned
+; MIPS32: or
+; MIPS32: or
+
+
 define internal i64 @xor64BitSigned(i64 %a, i64 %b) {
 entry:
   %xor = xor i64 %b, %a
@@ -672,6 +744,11 @@ entry:
 ; ARM32: eor
 ; ARM32: eor
 
+; MIPS32-LABEL: xor64BitSigned
+; MIPS32: xor
+; MIPS32: xor
+
+
 define internal i64 @xor64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %xor = xor i64 %b, %a
@@ -689,6 +766,10 @@ entry:
 ; ARM32: eor
 ; ARM32: eor
 
+; MIPS32-LABEL: xor64BitUnsigned
+; MIPS32: xor
+; MIPS32: xor
+
 define internal i32 @trunc64To32Signed(i64 %padding, i64 %a) {
 entry:
   %conv = trunc i64 %a to i32