Subzero: Mips: Lower some i64 arithmetic instructions

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_X8632 --command FileCheck --check-prefix=OPTM1 %s
 
 ; TODO(jvoung): Stop skipping unimplemented parts (via --skip-unimplemented)
 ; once enough infrastructure is in. Also, switch to --filetype=obj
 ; when possible.
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command %p2i --filetype=asm --assemble \
 ; RUN:   --disassemble --target arm32 -i %s --args -O2 --skip-unimplemented \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix ARM32 --check-prefix ARM32-O2 %s
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command %p2i --filetype=asm --assemble --disassemble --target arm32 \
 ; RUN:   -i %s --args -Om1 --skip-unimplemented \
 ; RUN:   -allow-externally-defined-symbols \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command FileCheck --check-prefix ARM32 --check-prefix ARM32-OM1 %s
 
+; TODO(rkotler): Stop skipping unimplemented parts (via --skip-unimplemented)
+; once enough infrastructure is in. Also, switch to --filetype=obj
+; when possible.
+; RUN: %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command %p2i --filetype=asm --assemble \
+; RUN:   --disassemble --target mips32 -i %s --args  -O2 --skip-unimplemented \
+; RUN:   -allow-externally-defined-symbols \
+; RUN:   | %if --need=target_MIPS32 --need=allow_dump \
+; RUN:   --command FileCheck --check-prefix MIPS32 --check-prefix MIPS32-O2 %s

[Jim Stichnoth, 2016/01/30 17:03:29]

TIL that FileCheck can take multiple --check-prefix arguments.  I wish I had
known about this before!

Three problems, though:

1. None of the check lines below use MIPS32-O2.

2. Many of the check lines below use MIPS which is not part of any RUN command.

3. You really need another RUN command that tests -Om1.

[rkotlerimgtec, 2016/01/30 23:48:31]

This just mimicks what ARM is doing here. -Om1 was not in the ARM
patch that this follows. There are some things regarding the stack that need to
be there that had not been implemented at this stage of ARM development.

[Jim Stichnoth, 2016/01/31 05:29:47]

All the same, using -Om1 exposes lowering/legalization problems (operands that
should be in registers but aren't) and this is an ideal setting to find and fix
them.

Spoiler alert: if you change it to -Om1 here and make all the other changes I
suggested, you will get a passing test. :)

+
 @__init_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__fini_array_start = internal constant [0 x i8] zeroinitializer, align 4
 @__tls_template_start = internal constant [0 x i8] zeroinitializer, align 8
 @__tls_template_alignment = internal constant [4 x i8] c"\01\00\00\00", align 4
 
 define internal i32 @ignore64BitArg(i64 %a, i32 %b, i64 %c) {
 entry:
   ret i32 %b
 }
 
+; MIPS32-LABEL: ignore64BitArg
+; MIPS: move v0,a2
+
 define internal i32 @pass64BitArg(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f) {
 entry:
   %call = call i32 @ignore64BitArgNoInline(i64 %a, i32 123, i64 %b)
   %call1 = call i32 @ignore64BitArgNoInline(i64 %c, i32 123, i64 %d)
   %call2 = call i32 @ignore64BitArgNoInline(i64 %e, i32 123, i64 %f)
   %add = add i32 %call1, %call
   %add3 = add i32 %add, %call2
   ret i32 %add3
 }
 ; CHECK-LABEL: pass64BitArg
@@ skipping 46 matching lines @@
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      mov     r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      str     {{.*}}, [sp]
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      mov     r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 
+; MIPS32-LABEL: pass64BitArg
+
 
 declare i32 @ignore64BitArgNoInline(i64, i32, i64)
 
 define internal i32 @pass64BitConstArg(i64 %a, i64 %b) {
 entry:
   %call = call i32 @ignore64BitArgNoInline(i64 %b, i32 123, i64 -2401053092306725256)
   ret i32 %call
 }
 ; CHECK-LABEL: pass64BitConstArg
 ; CHECK:      sub     esp
@@ skipping 45 matching lines @@
 ; OPTM1: mov DWORD PTR{{.*}},0x7b
 ; OPTM1: mov DWORD PTR{{.*}},0x0
 ; OPTM1: call {{.*}} R_{{.*}} ignore64BitArgNoInline
 ; ARM32-LABEL: pass64BitUndefArg
 ; ARM32: sub sp
 ; ARM32: mov {{.*}}, #0
 ; ARM32: str
 ; ARM32: mov {{.*}}, #123
 ; ARM32: bl {{.*}} ignore64BitArgNoInline
 
+; MIPS32-LABEL: pass64BitUndefArg
+; MIPS: jr  ra
+
 define internal i64 @return64BitArg(i64 %padding, i64 %a) {
 entry:
   ret i64 %a
 }
 ; CHECK-LABEL: return64BitArg
 ; CHECK: mov     {{.*}},DWORD PTR [esp+0xc]
 ; CHECK: mov     {{.*}},DWORD PTR [esp+0x10]
 ;
 ; OPTM1-LABEL: return64BitArg
 ; OPTM1: mov     {{.*}},DWORD PTR [esp+0xc]
 ; OPTM1: mov     {{.*}},DWORD PTR [esp+0x10]
 
 ; ARM32-LABEL: return64BitArg
 ; ARM32: mov {{.*}}, r2
 ; ARM32: mov {{.*}}, r3
 ; ARM32: bx lr
 
+; MIPS-LABEL; return64BitArg
+; MIPS: move v0,a2
+; MIPS: move v1,a3
+; MIPS: jr ra
+
 define internal i64 @return64BitConst() {
 entry:
   ret i64 -2401053092306725256
 }
 ; CHECK-LABEL: return64BitConst
 ; CHECK: mov     eax,0x12345678
 ; CHECK: mov     edx,0xdeadbeef
 ;
 ; OPTM1-LABEL: return64BitConst
 ; OPTM1: mov     eax,0x12345678
 ; OPTM1: mov     edx,0xdeadbeef
 
 ; ARM32-LABEL: return64BitConst
 ; ARM32: movw r0, #22136 ; 0x5678
 ; ARM32: movt r0, #4660  ; 0x1234
 ; ARM32: movw r1, #48879 ; 0xbeef
 ; ARM32: movt r1, #57005 ; 0xdead
 
+; MIPS32-LABEL: return64BitConst
+; MIPS32: lui v0,0x1234
+; MIPS32: ori v0,v0,0x5678
+; MIPS32: lui v1,0xdead
+; MIPS32: ori v1,v1,0xbeef
+; MIPS32: jr ra
+
 define internal i64 @add64BitSigned(i64 %a, i64 %b) {
 entry:
   %add = add i64 %b, %a
   ret i64 %add
 }
 ; CHECK-LABEL: add64BitSigned
 ; CHECK: add
 ; CHECK: adc
 ;
 ; OPTM1-LABEL: add64BitSigned
 ; OPTM1: add
 ; OPTM1: adc
 
 ; ARM32-LABEL: add64BitSigned
 ; ARM32: adds
 ; ARM32: adc
 
+; MIPS-LABEL: add64BitSigned
+; MIPS: addu
+; MIPS: sltu
+; MIPS: addu
+; MIPS: addu
+
 define internal i64 @add64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %add = add i64 %b, %a
   ret i64 %add
 }
 ; CHECK-LABEL: add64BitUnsigned
 ; CHECK: add
 ; CHECK: adc
 ;
 ; OPTM1-LABEL: add64BitUnsigned
 ; OPTM1: add
 ; OPTM1: adc
 
 ; ARM32-LABEL: add64BitUnsigned
 ; ARM32: adds
 ; ARM32: adc
 
+; MIPS-LABEL: add64BitUnsigned
+; MIPS: addu
+; MIPS: sltu
+; MIPS: addu
+; MIPS: addu
+
 define internal i64 @sub64BitSigned(i64 %a, i64 %b) {
 entry:
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
 ; CHECK-LABEL: sub64BitSigned
 ; CHECK: sub
 ; CHECK: sbb
 ;
 ; OPTM1-LABEL: sub64BitSigned
 ; OPTM1: sub
 ; OPTM1: sbb
 
 ; ARM32-LABEL: sub64BitSigned
 ; ARM32: subs
 ; ARM32: sbc
 
+; MIPS-LABEL: sub64BitSigned
+; MIPS: subu
+; MIPS: sltu
+; MIPS: addu
+; MIPS: subu
+
 define internal i64 @sub64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %sub = sub i64 %a, %b
   ret i64 %sub
 }
 ; CHECK-LABEL: sub64BitUnsigned
 ; CHECK: sub
 ; CHECK: sbb
 ;
 ; OPTM1-LABEL: sub64BitUnsigned
 ; OPTM1: sub
 ; OPTM1: sbb
 
 ; ARM32-LABEL: sub64BitUnsigned
 ; ARM32: subs
 ; ARM32: sbc
 
+; MIPS-LABEL: sub64BitUnsigned
+; MIPS: subu
+; MIPS: sltu
+; MIPS: addu
+; MIPS: subu
+
 define internal i64 @mul64BitSigned(i64 %a, i64 %b) {
 entry:
   %mul = mul i64 %b, %a
   ret i64 %mul
 }
 ; CHECK-LABEL: mul64BitSigned
 ; CHECK: imul
 ; CHECK: mul
 ; CHECK: add
 ; CHECK: imul
@@ skipping 314 matching lines @@
 ; CHECK: and
 ;
 ; OPTM1-LABEL: and64BitSigned
 ; OPTM1: and
 ; OPTM1: and
 
 ; ARM32-LABEL: and64BitSigned
 ; ARM32: and
 ; ARM32: and
 
+; MIPS32-LABEL: and64BitSigned
+; MIPS32: and
+; MIPS32: and
+
 define internal i64 @and64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %and = and i64 %b, %a
   ret i64 %and
 }
 ; CHECK-LABEL: and64BitUnsigned
 ; CHECK: and
 ; CHECK: and
 ;
 ; OPTM1-LABEL: and64BitUnsigned
 ; OPTM1: and
 ; OPTM1: and
 
 ; ARM32-LABEL: and64BitUnsigned
 ; ARM32: and
 ; ARM32: and
 
+; MIPS32-LABEL: and64BitUnsigned
+; MIPS32: and
+; MIPS32: and
+
 define internal i64 @or64BitSigned(i64 %a, i64 %b) {
 entry:
   %or = or i64 %b, %a
   ret i64 %or
 }
 ; CHECK-LABEL: or64BitSigned
 ; CHECK: or
 ; CHECK: or
 ;
 ; OPTM1-LABEL: or64BitSigned
 ; OPTM1: or
 ; OPTM1: or
 
 ; ARM32-LABEL: or64BitSigned
 ; ARM32: orr
 ; ARM32: orr
 
+; MIPS32-LABEL: or64BitSigned
+; MIPS32: or
+; MIPS32: or
+
+

[Jim Stichnoth, 2016/01/30 17:03:29]

This and the next two tests add 2 blank lines instead of 1...

[rkotlerimgtec, 2016/01/30 23:48:31]

Done.

 define internal i64 @or64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %or = or i64 %b, %a
   ret i64 %or
 }
 ; CHECK-LABEL: or64BitUnsigned
 ; CHECK: or
 ; CHECK: or
 ;
 ; OPTM1-LABEL: or64BitUnsigned
 ; OPTM1: or
 ; OPTM1: or
 
 ; ARM32-LABEL: or64BitUnsigned
 ; ARM32: orr
 ; ARM32: orr
 
+; MIPS32-LABEL: or64BitUnsigned
+; MIPS32: or
+; MIPS32: or
+
+
 define internal i64 @xor64BitSigned(i64 %a, i64 %b) {
 entry:
   %xor = xor i64 %b, %a
   ret i64 %xor
 }
 ; CHECK-LABEL: xor64BitSigned
 ; CHECK: xor
 ; CHECK: xor
 ;
 ; OPTM1-LABEL: xor64BitSigned
 ; OPTM1: xor
 ; OPTM1: xor
 
 ; ARM32-LABEL: xor64BitSigned
 ; ARM32: eor
 ; ARM32: eor
 
+; MIPS32-LABEL: xor64BitSigned
+; MIPS32: xor
+; MIPS32: xor
+
+
 define internal i64 @xor64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %xor = xor i64 %b, %a
   ret i64 %xor
 }
 ; CHECK-LABEL: xor64BitUnsigned
 ; CHECK: xor
 ; CHECK: xor
 ;
 ; OPTM1-LABEL: xor64BitUnsigned
 ; OPTM1: xor
 ; OPTM1: xor
 
 ; ARM32-LABEL: xor64BitUnsigned
 ; ARM32: eor
 ; ARM32: eor
 
+; MIPS32-LABEL: xor64BitUnsigned
+; MIPS32: xor
+; MIPS32: xor
+
 define internal i32 @trunc64To32Signed(i64 %padding, i64 %a) {
 entry:
   %conv = trunc i64 %a to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: trunc64To32Signed
 ; CHECK: mov     eax,DWORD PTR [esp+0xc]
 ;
 ; OPTM1-LABEL: trunc64To32Signed
 ; OPTM1: mov     eax,DWORD PTR [esp+
@@ skipping 1150 matching lines @@
 ; CHECK-LABEL: phi64Undef
 ; CHECK: mov {{.*}},0x0
 ; CHECK: mov {{.*}},0x0
 ; OPTM1-LABEL: phi64Undef
 ; OPTM1: mov {{.*}},0x0
 ; OPTM1: mov {{.*}},0x0
 ; ARM32-LABEL: phi64Undef
 ; ARM32: mov {{.*}} #0
 ; ARM32: mov {{.*}} #0