Add the VMRS instruction to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 00f2a80b7647f9c616355033e1705f415740197f..61ce36787387f4e307933f15e9a8ad91196114de 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -2382,7 +2382,7 @@ void AssemblerARM32::vldrs(const Operand *OpSd, const Operand *OpAddress,
 void AssemblerARM32::vmovsr(const Operand *OpSn, const Operand *OpRt,
                             CondARM32::Cond Cond) {
   // VMOV (between ARM core register and single-precision register)
-  //   ARM seciont A8.8.343, encoding A1.
+  //   ARM section A8.8.343, encoding A1.
   //
   //   vmov<c> <Sn>, <Rt>
   //
@@ -2400,6 +2400,20 @@ void AssemblerARM32::vmovsr(const Operand *OpSn, const Operand *OpRt,
   emitInst(Encoding);
 }
 
+void AssemblerARM32::vmrsAPSR_nzcv(CondARM32::Cond Cond) {
+  // MVRS - ARM section A*.8.348, encoding A1:
+  //   vmrs<c> APSR_nzcv, FPSCR
+  //
+  // cccc111011110001tttt101000010000 where tttt=0x15 (i.e. when Rt=pc, use
+  // APSR_nzcv instead).
+  assert(CondARM32::isDefined(Cond));
+  IValueT Encoding = B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 | B15 | B14 |
+                     B13 | B12 | B11 | B9 | B4 |
+                     (encodeCondition(Cond) << kConditionShift);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::vmuls(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VMUL (floating-point) - ARM section A8.8.351, encoding A2: