Add the VMRS instruction to the integrated ARM assembler.

src/IceAssemblerARM32.cpp

 //===- subzero/src/IceAssemblerARM32.cpp - Assembler for ARM32 --*- C++ -*-===//
 //
 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 //
 // Modified by the Subzero authors.
 //
 //===----------------------------------------------------------------------===//
 //
@@ skipping 2364 matching lines @@
   IValueT Encoding = B27 | B26 | B24 | B20 | B11 | B9 |
                      (encodeCondition(Cond) << kConditionShift) |
                      (getYInRegXXXXY(Sd) << 22) |
                      (getXXXXInRegXXXXY(Sd) << 12) | Address;
   emitInst(Encoding);
 }
 
 void AssemblerARM32::vmovsr(const Operand *OpSn, const Operand *OpRt,
                             CondARM32::Cond Cond) {
   // VMOV (between ARM core register and single-precision register)
-  //   ARM seciont A8.8.343, encoding A1.
+  //   ARM section A8.8.343, encoding A1.
   //
   //   vmov<c> <Sn>, <Rt>
   //
   // cccc1110000onnnntttt1010N0010000 where cccc=Cond, nnnnN = Sn, and tttt=Rt.
   constexpr const char *Vmovsr = "vmovsr";
   IValueT Sn = encodeSRegister(OpSn, "Sn", Vmovsr);
   IValueT Rt = encodeGPRegister(OpRt, "Rt", Vmovsr);
   assert(Sn < RegARM32::getNumSRegs());
   assert(Rt < RegARM32::getNumGPRegs());
   assert(CondARM32::isDefined(Cond));
   AssemblerBuffer::EnsureCapacity ensured(&Buffer);
   IValueT Encoding = (encodeCondition(Cond) << kConditionShift) | B27 | B26 |
                      B25 | B11 | B9 | B4 | (getXXXXInRegXXXXY(Sn) << 16) |
                      (Rt << kRdShift) | (getYInRegXXXXY(Sn) << 7);
   emitInst(Encoding);
 }
 
+void AssemblerARM32::vmrsAPSR_nzcv(CondARM32::Cond Cond) {
+  // MVRS - ARM section A*.8.348, encoding A1:
+  //   vmrs<c> APSR_nzcv, FPSCR
+  //
+  // cccc111011110001tttt101000010000 where tttt=0x15 (i.e. when Rt=pc, use
+  // APSR_nzcv instead).
+  assert(CondARM32::isDefined(Cond));
+  IValueT Encoding = B27 | B26 | B25 | B23 | B22 | B21 | B20 | B16 | B15 | B14 |
+                     B13 | B12 | B11 | B9 | B4 |
+                     (encodeCondition(Cond) << kConditionShift);
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  emitInst(Encoding);
+}
+
 void AssemblerARM32::vmuls(const Operand *OpSd, const Operand *OpSn,
                            const Operand *OpSm, CondARM32::Cond Cond) {
   // VMUL (floating-point) - ARM section A8.8.351, encoding A2:
   //   vmul<c>.f32 <Sd>, <Sn>, <Sm>
   //
   // cccc11100D10nnnndddd101sN0M0mmmm where cccc=Cond, s=0, ddddD=Rd, nnnnN=Rn,
   // and mmmmM=Rm.
   constexpr const char *Vmuls = "vmuls";
   IValueT Sd = encodeSRegister(OpSd, "Sd", Vmuls);
   IValueT Sn = encodeSRegister(OpSn, "Sn", Vmuls);
@@ skipping 134 matching lines @@
   //
   // cccc11010D101101dddd1010iiiiiiii where cccc=Cond, ddddD=BaseReg, and
   // iiiiiiii=NumConsecRegs.
   constexpr IValueT VpushOpcode =
       B27 | B26 | B24 | B21 | B19 | B18 | B16 | B11 | B9;
   emitVStackOp(Cond, VpushOpcode, OpBaseReg, NumConsecRegs);
 }
 
 } // end of namespace ARM32
 } // end of namespace Ice