Add the VMRS instruction to the integrated ARM assembler.

tests_lit/assembler/arm32/vmrs.ll

Index: tests_lit/assembler/arm32/vmrs.ll
diff --git a/tests_lit/assembler/arm32/vmov-cast.ll b/tests_lit/assembler/arm32/vmrs.ll
similarity index 65%
copy from tests_lit/assembler/arm32/vmov-cast.ll
copy to tests_lit/assembler/arm32/vmrs.ll
index 2fa59d14ee3757b64e773531643e0b4cdf3d9b8d..ad6552a2165d22adae9923474a023dffbbab2961 100644
--- a/tests_lit/assembler/arm32/vmov-cast.ll
+++ b/tests_lit/assembler/arm32/vmrs.ll
@@ -1,6 +1,4 @@
-; Show that we know how to translate vmov for casts.
-
-; NOTE: Restricts S register to one that will better test S register encodings.
+; Test the "vmrs APSR_nzcv, FPSCR" form of the VMRS instruction.
 
 ; REQUIRES: allow_dump
 
@@ -26,20 +24,19 @@
 ; RUN:   -reg-use s20,s22,d20,d22 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
-define internal float @castToFloat(i32 %a) {
-; ASM-LABEL: castToFloat:
-; DIS-LABEL: 00000000 <castToFloat>:
-; IASM-LABEL: castToFloat:
+define internal i32 @testVmrsASPR_nzcv() {
+; ASM-LABEL: testVmrsASPR_nzcv:
+; DIS-LABEL: 00000000 <testVmrsASPR_nzcv>:
 
 entry:
-; ASM: .LcastToFloat$entry:
-; IASM: .LcastToFloat$entry:
+; ASM: .LtestVmrsASPR_nzcv$entry:
 
-  %0 = bitcast i32 %a to float
+  %test = fcmp olt float 0.0, 0.0
 
-; ASM:          vmov    s20, r0
-; DIS:  10:     ee0a0a10
-; IASM-NOT:     vmov
+; ASM:  vmrs    APSR_nzcv, FPSCR
+; DIS:   18:    eef1fa10
+; IASM-NOT: vmrs
 
-  ret float %0
+  %result = zext i1 %test to i32
+  ret i32 %result
 }