Add the VMRS instruction to the integrated ARM assembler.

tests_lit/assembler/arm32/vmrs.ll

-; Show that we know how to translate vmov for casts.
+; Test the "vmrs APSR_nzcv, FPSCR" form of the VMRS instruction.
 
-; NOTE: Restricts S register to one that will better test S register encodings.
-
 ; REQUIRES: allow_dump
 
 ; Compile using standalone assembler.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --args -Om1 \
 ; RUN:   -reg-use s20,s22,d20,d22 \

[Jim Stichnoth, 2016/01/25 16:48:45]

Do you need the -reg-use lines if you aren't testing for those register
encodings?

It's fine to leave those args if you have a general plan to use consistent
register sets across all tests.

[Karl, 2016/01/25 17:17:44]

Good point. I forgot about the register argument when copying. Since the
instruction doesn't use any registers controlled by the register allocator,
removing the argument.

 ; RUN:   | FileCheck %s --check-prefix=ASM
 
 ; Show bytes in assembled standalone code.
 ; RUN: %p2i --filetype=asm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
 ; RUN:   -reg-use s20,s22,d20,d22 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
 ; Compile using integrated assembler.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --args -Om1 \
 ; RUN:   -reg-use s20,s22,d20,d22 \
 ; RUN:   | FileCheck %s --check-prefix=IASM
 
 ; Show bytes in assembled integrated code.
 ; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
 ; RUN:   --args -Om1 \
 ; RUN:   -reg-use s20,s22,d20,d22 \
 ; RUN:   | FileCheck %s --check-prefix=DIS
 
-define internal float @castToFloat(i32 %a) {
-; ASM-LABEL: castToFloat:
-; DIS-LABEL: 00000000 <castToFloat>:
-; IASM-LABEL: castToFloat:
+define internal i32 @testVmrsASPR_nzcv() {
+; ASM-LABEL: testVmrsASPR_nzcv:
+; DIS-LABEL: 00000000 <testVmrsASPR_nzcv>:
 
 entry:
-; ASM: .LcastToFloat$entry:
-; IASM: .LcastToFloat$entry:
+; ASM: .LtestVmrsASPR_nzcv$entry:
 
-  %0 = bitcast i32 %a to float
+  %test = fcmp olt float 0.0, 0.0
 
-; ASM:          vmov    s20, r0
-; DIS:  10:     ee0a0a10
-; IASM-NOT:     vmov
+; ASM:  vmrs    APSR_nzcv, FPSCR
+; DIS:   18:    eef1fa10
+; IASM-NOT: vmrs
 
-  ret float %0
+  %result = zext i1 %test to i32
+  ret i32 %result
 }