MIPS: Use PC realitive instructions on r6.

test/cctest/test-macro-assembler-mips64.cc

Index: test/cctest/test-macro-assembler-mips64.cc
diff --git a/test/cctest/test-macro-assembler-mips64.cc b/test/cctest/test-macro-assembler-mips64.cc
index 684b554236c123d3c3083fda744a7454a6b0f8e8..6cac726c212778a3f0749726c84a752b6d345e14 100644
--- a/test/cctest/test-macro-assembler-mips64.cc
+++ b/test/cctest/test-macro-assembler-mips64.cc
@@ -323,21 +323,22 @@ TEST(jump_tables5) {
   Label labels[kNumCases];
   Label done;
 
-  __ daddiu(sp, sp, -8);
-  __ sd(ra, MemOperand(sp));
+  __ Push(ra);
+
+  // Opposite of Align(8) as we have unaligned number of instructions in the
+  // following block before the first dd().

[ivica.bogosavljevic, 2016/01/25 11:40:03]

Already made a remark

[balazs.kilvady, 2016/01/25 12:46:17]

So do I :)

+  if ((masm->pc_offset() & 7) == 0) {
+    __ nop();
+  }
 
-  __ Align(8);
   {
-    __ BlockTrampolinePoolFor(kNumCases * 2 + 7 + 1);
+    __ BlockTrampolinePoolFor(kNumCases * 2 + 6 + 1);
     PredictableCodeSizeScope predictable(
-        masm, kNumCases * kPointerSize + ((7 + 1) * Assembler::kInstrSize));
-    Label here;
+        masm, kNumCases * kPointerSize + ((6 + 1) * Assembler::kInstrSize));
 
-    __ bal(&here);
-    __ dsll(at, a0, 3);  // In delay slot.
-    __ bind(&here);
-    __ daddu(at, at, ra);
-    __ ld(at, MemOperand(at, 6 * Assembler::kInstrSize));
+    __ addiupc(at, 6 + 1);
+    __ dlsa(at, at, a0, 3);
+    __ ld(at, MemOperand(at));
     __ jalr(at);
     __ nop();  // Branch delay slot nop.
     __ bc(&done);
@@ -351,15 +352,13 @@ TEST(jump_tables5) {
 
   for (int i = 0; i < kNumCases; ++i) {
     __ bind(&labels[i]);
-    __ lui(v0, (values[i] >> 16) & 0xffff);
-    __ ori(v0, v0, values[i] & 0xffff);
+    __ li(v0, values[i]);
     __ jr(ra);
     __ nop();
   }
 
   __ bind(&done);
-  __ ld(ra, MemOperand(sp));
-  __ daddiu(sp, sp, 8);
+  __ Pop(ra);
   __ jr(ra);
   __ nop();