MIPS: Use PC realitive instructions on r6.

src/compiler/mips64/code-generator-mips64.cc

Index: src/compiler/mips64/code-generator-mips64.cc
diff --git a/src/compiler/mips64/code-generator-mips64.cc b/src/compiler/mips64/code-generator-mips64.cc
index 1b81aa569808a05aed90d94ee8305f38c81c3c12..c0dc5f5ada2d2eedf5ab2e72b8f2b3558e2c1838 100644
--- a/src/compiler/mips64/code-generator-mips64.cc
+++ b/src/compiler/mips64/code-generator-mips64.cc
@@ -1653,17 +1653,28 @@ void CodeGenerator::AssembleArchTableSwitch(Instruction* instr) {
   MipsOperandConverter i(this, instr);
   Register input = i.InputRegister(0);
   size_t const case_count = instr->InputCount() - 2;
-  Label here;
 
   __ Branch(GetLabel(i.InputRpo(1)), hs, input, Operand(case_count));
   __ BlockTrampolinePoolFor(static_cast<int>(case_count) * 2 + 7);
-  // Ensure that dd-ed labels use 8 byte aligned addresses.
-  __ Align(8);
-  __ bal(&here);
-  __ dsll(at, input, 3);  // Branch delay slot.
-  __ bind(&here);
-  __ daddu(at, at, ra);
-  __ ld(at, MemOperand(at, 4 * v8::internal::Assembler::kInstrSize));
+  // Ensure that dd-ed labels use 8 bytes aligned addresses.
+  if (kArchVariant >= kMips64r6) {

[ivica.bogosavljevic, 2016/01/25 11:40:03]

Also,  I am not sure if this is a best way to do this. What do you think,
instead of this, we introduce a macro
#define MipsArchVairantGreaterEqual(X) or something similar and use it?

[balazs.kilvady, 2016/01/25 12:46:17]

 if (VERSION >= 7) {}
code is quite common in several projects so I am OK with any kind of similar
solution just we have to agree and follow the agrement :)

+    // Opposite of Align(8) as we have unaligned number of instructions before
+    // the first dd().
+    if ((masm()->pc_offset() & 7) == 0) {

[ivica.bogosavljevic, 2016/01/25 11:40:03]

I think you should call Align(8) + additional nop() after this instead of this,
because this code wouldn't work correctly if previous instruction were compact
branch. In that case calling Aling would emit the instruction pending for
forbidden slot.

[balazs.kilvady, 2016/01/25 12:46:17]

I don't think so. We don't need 1 or 2 nops as addiupc is not a CTI. In the case
of a previous compact branch it does not matter if there is a nop before
addiupc.

[ivica.bogosavljevic, 2016/01/26 08:32:29]

I am not sure what to think about this. On one hand, you save one instruction if
you do it this way. On the other hand, if somebody new would use this code as a
template to implement unalign, he would run into problems if instruction
following this unalign were a branch-compact.

Personally, I would prefer to have some Unalign macro or something similar.
Unless the code is used really often, saving one instruction doesn't bring a lot
and has a potential to create problems in the future.

On 2016/01/25 12:46:17, balazs.kilvady wrote:

[balazs.kilvady, 2016/01/26 18:40:05]

I see.
I created a macro to hide (behind MacroAssembler) the dangerous align code. I
don't think we win too much with this solution but fun to implement and I learn
how to use PC relative instruction(s) :)

+      __ nop();
+    }
+    __ addiupc(at, 5);
+    __ dlsa(at, at, input, 3);
+    __ ld(at, MemOperand(at));
+  } else {
+    Label here;
+    __ Align(8);
+    __ bal(&here);
+    __ dsll(at, input, 3);  // Branch delay slot.
+    __ bind(&here);
+    __ daddu(at, at, ra);
+    __ ld(at, MemOperand(at, 4 * v8::internal::Assembler::kInstrSize));
+  }
   __ jr(at);
   __ nop();  // Branch delay slot nop.
   for (size_t index = 0; index < case_count; ++index) {