Add VMOV(immediate) instructions to the ARM assembler.

Add VMOV(immediate) instructions to the ARM assembler.

Adds the vmovs/vmovd instructions to the integerated ARM assembler.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Committed: https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a=commit;h=c64448fbaf1dca1495a55e6c085555ca637e3e74

[Karl, 2016-01-25 23:29:46]

Description was changed from

==========
Add VMOV(immediate) instructions to the ARM assembler.

Adds the vmovs/vmovd instructions to the integerated ARM assembler.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
==========

to

==========
Add VMOV(immediate) instructions to the ARM assembler.

Adds the vmovs/vmovd instructions to the integerated ARM assembler.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
==========

[Karl, 2016-01-25 23:29:46]

kschimpf@google.com changed reviewers:
+ eholk@chromium.org, jpp@chromium.org, sehr@chromium.org, stichnot@chromium.org

[Jim Stichnoth, 2016-01-26 13:44:41]

https://codereview.chromium.org/1624383004/diff/20001/src/IceAssemblerARM32.cpp
File src/IceAssemblerARM32.cpp (right):

https://codereview.chromium.org/1624383004/diff/20001/src/IceAssemblerARM32.c...
src/IceAssemblerARM32.cpp:2369: IValueT OpcodePlusImm8 = VmovsOpcode | ((Imm8 >>
4) << 16) | (Imm8 & 0xf);
I see that the ModifiedImm is being swizzled into the encoded instruction.  For
your tests, could you find an encodable floating-point constant where the lower
half and the upper half of the Imm8 are both nonzero?  Similar to the way other
tests try to force specific register numbers.

https://codereview.chromium.org/1624383004/diff/20001/src/IceInstARM32.cpp
File src/IceInstARM32.cpp (right):

https://codereview.chromium.org/1624383004/diff/20001/src/IceInstARM32.cpp#ne...
src/IceInstARM32.cpp:1133: assert(false);
assert(false && "some message");

https://codereview.chromium.org/1624383004/diff/20001/src/IceInstARM32.h
File src/IceInstARM32.h (right):

https://codereview.chromium.org/1624383004/diff/20001/src/IceInstARM32.h#newc...
src/IceInstARM32.h:274: uint32_t ModifiedImm;
const

[Karl, 2016-01-26 16:42:05]

https://codereview.chromium.org/1624383004/diff/20001/src/IceAssemblerARM32.cpp
File src/IceAssemblerARM32.cpp (right):

https://codereview.chromium.org/1624383004/diff/20001/src/IceAssemblerARM32.c...
src/IceAssemblerARM32.cpp:2369: IValueT OpcodePlusImm8 = VmovsOpcode | ((Imm8 >>
4) << 16) | (Imm8 & 0xf);
On 2016/01/26 13:44:41, stichnot wrote:
> I see that the ModifiedImm is being swizzled into the encoded instruction. 
For
> your tests, could you find an encodable floating-point constant where the
lower
> half and the upper half of the Imm8 are both nonzero?  Similar to the way
other
> tests try to force specific register numbers.

Done.

https://codereview.chromium.org/1624383004/diff/20001/src/IceInstARM32.cpp
File src/IceInstARM32.cpp (right):

https://codereview.chromium.org/1624383004/diff/20001/src/IceInstARM32.cpp#ne...
src/IceInstARM32.cpp:1133: assert(false);
On 2016/01/26 13:44:41, stichnot wrote:
> assert(false && "some message");

Done.

https://codereview.chromium.org/1624383004/diff/20001/src/IceInstARM32.h
File src/IceInstARM32.h (right):

https://codereview.chromium.org/1624383004/diff/20001/src/IceInstARM32.h#newc...
src/IceInstARM32.h:274: uint32_t ModifiedImm;
On 2016/01/26 13:44:41, stichnot wrote:
> const

Done.

[Jim Stichnoth, 2016-01-26 17:37:36]

lgtm

https://codereview.chromium.org/1624383004/diff/40001/tests_lit/assembler/arm...
File tests_lit/assembler/arm32/vmov-imm.ll (right):

https://codereview.chromium.org/1624383004/diff/40001/tests_lit/assembler/arm...
tests_lit/assembler/arm32/vmov-imm.ll:29: store double 1.5, double* %addr, align
8
BTW, you can make this test even simpler by dropping the inttoptr instruction
and using:

  store double 1.5, double* undef, align 8

[Karl, 2016-01-26 19:12:32]

Description was changed from

==========
Add VMOV(immediate) instructions to the ARM assembler.

Adds the vmovs/vmovd instructions to the integerated ARM assembler.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
==========

to

==========
Add VMOV(immediate) instructions to the ARM assembler.

Adds the vmovs/vmovd instructions to the integerated ARM assembler.

BUG= https://bugs.chromium.org/p/nativeclient/issues/detail?id=4334
R=stichnot@chromium.org

Committed:
https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a...
==========

[Karl, 2016-01-26 19:12:34]

Committed patchset #3 (id:40001) manually as
c64448fbaf1dca1495a55e6c085555ca637e3e74 (presubmit successful).

[Karl, 2016-01-26 19:12:48]

https://codereview.chromium.org/1624383004/diff/40001/tests_lit/assembler/arm...
File tests_lit/assembler/arm32/vmov-imm.ll (right):

https://codereview.chromium.org/1624383004/diff/40001/tests_lit/assembler/arm...
tests_lit/assembler/arm32/vmov-imm.ll:29: store double 1.5, double* %addr, align
8
On 2016/01/26 17:37:36, stichnot wrote:
> BTW, you can make this test even simpler by dropping the inttoptr instruction
> and using:
> 
>   store double 1.5, double* undef, align 8

Surprisingly, this causes a pnacl-freeze error for the float case. For now,
leaving as is. Will look into why pnacl-freeze is failing.