[turbofan] Implement rounding of floats on x64 and ia32 without sse4.1.

src/compiler/ia32/instruction-selector-ia32.cc

Index: src/compiler/ia32/instruction-selector-ia32.cc
diff --git a/src/compiler/ia32/instruction-selector-ia32.cc b/src/compiler/ia32/instruction-selector-ia32.cc
index fa21d52d1565d6d377cfeebc7c4cefbdd6906676..7dad4f635fba240a2ccffbac81ce9e80d983fc91 100644
--- a/src/compiler/ia32/instruction-selector-ia32.cc
+++ b/src/compiler/ia32/instruction-selector-ia32.cc
@@ -785,8 +785,17 @@ void InstructionSelector::VisitFloat64Sub(Node* node) {
           CanCover(m.right().node(), m.right().InputAt(0))) {
         Float64BinopMatcher mright0(m.right().InputAt(0));
         if (mright0.left().IsMinusZero()) {
-          Emit(kSSEFloat64Round | MiscField::encode(kRoundUp),
-               g.DefineAsRegister(node), g.UseRegister(mright0.right().node()));
+          if (CpuFeatures::IsSupported(SSE4_1)) {
+            Emit(kSSEFloat64Round | MiscField::encode(kRoundUp),
+                 g.DefineAsRegister(node),
+                 g.UseRegister(mright0.right().node()));
+          } else {
+            IA32OperandGenerator g(this);
+            InstructionOperand temps[] = {g.TempRegister()};
+            Emit(kSSEFloat64Round | MiscField::encode(kRoundUp),
+                 g.DefineAsRegister(node),
+                 g.UseRegister(mright0.right().node()), 1, temps);
+          }
           return;
         }
       }
@@ -871,32 +880,74 @@ void InstructionSelector::VisitFloat64Sqrt(Node* node) {
 
 
 void InstructionSelector::VisitFloat32RoundDown(Node* node) {
-  VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundDown));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundDown));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat32Round | MiscField::encode(kRoundDown),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat64RoundDown(Node* node) {
-  VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundDown));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundDown));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat64Round | MiscField::encode(kRoundDown),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat32RoundUp(Node* node) {
-  VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundUp));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundUp));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat32Round | MiscField::encode(kRoundUp),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat64RoundUp(Node* node) {
-  VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundUp));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundUp));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat64Round | MiscField::encode(kRoundUp),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat32RoundTruncate(Node* node) {
-  VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundToZero));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundToZero));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat32Round | MiscField::encode(kRoundToZero),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat64RoundTruncate(Node* node) {
-  VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundToZero));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundToZero));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat64Round | MiscField::encode(kRoundToZero),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
@@ -906,12 +957,26 @@ void InstructionSelector::VisitFloat64RoundTiesAway(Node* node) {
 
 
 void InstructionSelector::VisitFloat32RoundTiesEven(Node* node) {
-  VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundToNearest));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundToNearest));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat32Round | MiscField::encode(kRoundToNearest),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat64RoundTiesEven(Node* node) {
-  VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundToNearest));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundToNearest));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat64Round | MiscField::encode(kRoundToNearest),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
@@ -1323,20 +1388,19 @@ InstructionSelector::SupportedMachineOperatorFlags() {
       MachineOperatorBuilder::kFloat64Max |
       MachineOperatorBuilder::kFloat64Min |
       MachineOperatorBuilder::kWord32ShiftIsSafe |
-      MachineOperatorBuilder::kWord32Ctz;
+      MachineOperatorBuilder::kWord32Ctz |
+      MachineOperatorBuilder::kFloat32RoundDown |
+      MachineOperatorBuilder::kFloat32RoundUp |
+      MachineOperatorBuilder::kFloat32RoundTruncate |
+      MachineOperatorBuilder::kFloat32RoundTiesEven |
+      MachineOperatorBuilder::kFloat64RoundDown |
+      MachineOperatorBuilder::kFloat64RoundUp |
+      MachineOperatorBuilder::kFloat64RoundTruncate |
+      MachineOperatorBuilder::kFloat64RoundTiesEven;
+
   if (CpuFeatures::IsSupported(POPCNT)) {
     flags |= MachineOperatorBuilder::kWord32Popcnt;
   }
-  if (CpuFeatures::IsSupported(SSE4_1)) {
-    flags |= MachineOperatorBuilder::kFloat32RoundDown |
-             MachineOperatorBuilder::kFloat64RoundDown |
-             MachineOperatorBuilder::kFloat32RoundUp |
-             MachineOperatorBuilder::kFloat64RoundUp |
-             MachineOperatorBuilder::kFloat32RoundTruncate |
-             MachineOperatorBuilder::kFloat64RoundTruncate |
-             MachineOperatorBuilder::kFloat32RoundTiesEven |
-             MachineOperatorBuilder::kFloat64RoundTiesEven;
-  }
   return flags;
 }