[turbofan] Implement rounding of floats on x64 and ia32 without sse4.1.

src/compiler/ia32/instruction-selector-ia32.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/base/adapters.h"
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
 namespace v8 {
@@ skipping 767 matching lines @@
 void InstructionSelector::VisitFloat64Sub(Node* node) {
   IA32OperandGenerator g(this);
   Float64BinopMatcher m(node);
   if (m.left().IsMinusZero()) {
     if (m.right().IsFloat64RoundDown() &&
         CanCover(m.node(), m.right().node())) {
       if (m.right().InputAt(0)->opcode() == IrOpcode::kFloat64Sub &&
           CanCover(m.right().node(), m.right().InputAt(0))) {
         Float64BinopMatcher mright0(m.right().InputAt(0));
         if (mright0.left().IsMinusZero()) {
-          Emit(kSSEFloat64Round | MiscField::encode(kRoundUp),
-               g.DefineAsRegister(node), g.UseRegister(mright0.right().node()));
+          if (CpuFeatures::IsSupported(SSE4_1)) {
+            Emit(kSSEFloat64Round | MiscField::encode(kRoundUp),
+                 g.DefineAsRegister(node),
+                 g.UseRegister(mright0.right().node()));
+          } else {
+            IA32OperandGenerator g(this);
+            InstructionOperand temps[] = {g.TempRegister()};
+            Emit(kSSEFloat64Round | MiscField::encode(kRoundUp),
+                 g.DefineAsRegister(node),
+                 g.UseRegister(mright0.right().node()), 1, temps);
+          }
           return;
         }
       }
     }
     VisitFloatUnop(this, node, m.right().node(), kAVXFloat64Neg,
                    kSSEFloat64Neg);
     return;
   }
   VisitRROFloat(this, node, kAVXFloat64Sub, kSSEFloat64Sub);
 }
@@ skipping 64 matching lines @@
   VisitRO(this, node, kSSEFloat32Sqrt);
 }
 
 
 void InstructionSelector::VisitFloat64Sqrt(Node* node) {
   VisitRO(this, node, kSSEFloat64Sqrt);
 }
 
 
 void InstructionSelector::VisitFloat32RoundDown(Node* node) {
-  VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundDown));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundDown));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat32Round | MiscField::encode(kRoundDown),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat64RoundDown(Node* node) {
-  VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundDown));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundDown));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat64Round | MiscField::encode(kRoundDown),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat32RoundUp(Node* node) {
-  VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundUp));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundUp));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat32Round | MiscField::encode(kRoundUp),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat64RoundUp(Node* node) {
-  VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundUp));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundUp));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat64Round | MiscField::encode(kRoundUp),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat32RoundTruncate(Node* node) {
-  VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundToZero));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundToZero));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat32Round | MiscField::encode(kRoundToZero),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat64RoundTruncate(Node* node) {
-  VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundToZero));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundToZero));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat64Round | MiscField::encode(kRoundToZero),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat64RoundTiesAway(Node* node) {
   UNREACHABLE();
 }
 
 
 void InstructionSelector::VisitFloat32RoundTiesEven(Node* node) {
-  VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundToNearest));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundToNearest));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat32Round | MiscField::encode(kRoundToNearest),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::VisitFloat64RoundTiesEven(Node* node) {
-  VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundToNearest));
+  if (CpuFeatures::IsSupported(SSE4_1)) {
+    VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundToNearest));
+  } else {
+    IA32OperandGenerator g(this);
+    InstructionOperand temps[] = {g.TempRegister()};
+    Emit(kSSEFloat64Round | MiscField::encode(kRoundToNearest),
+         g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), 1, temps);
+  }
 }
 
 
 void InstructionSelector::EmitPrepareArguments(
     ZoneVector<PushParameter>* arguments, const CallDescriptor* descriptor,
     Node* node) {
   IA32OperandGenerator g(this);
 
   // Prepare for C function call.
   if (descriptor->IsCFunctionCall()) {
@@ skipping 391 matching lines @@
 
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
   MachineOperatorBuilder::Flags flags =
       MachineOperatorBuilder::kFloat32Max |
       MachineOperatorBuilder::kFloat32Min |
       MachineOperatorBuilder::kFloat64Max |
       MachineOperatorBuilder::kFloat64Min |
       MachineOperatorBuilder::kWord32ShiftIsSafe |
-      MachineOperatorBuilder::kWord32Ctz;
+      MachineOperatorBuilder::kWord32Ctz |
+      MachineOperatorBuilder::kFloat32RoundDown |
+      MachineOperatorBuilder::kFloat32RoundUp |
+      MachineOperatorBuilder::kFloat32RoundTruncate |
+      MachineOperatorBuilder::kFloat32RoundTiesEven |
+      MachineOperatorBuilder::kFloat64RoundDown |
+      MachineOperatorBuilder::kFloat64RoundUp |
+      MachineOperatorBuilder::kFloat64RoundTruncate |
+      MachineOperatorBuilder::kFloat64RoundTiesEven;
+
   if (CpuFeatures::IsSupported(POPCNT)) {
     flags |= MachineOperatorBuilder::kWord32Popcnt;
   }
-  if (CpuFeatures::IsSupported(SSE4_1)) {
-    flags |= MachineOperatorBuilder::kFloat32RoundDown |
-             MachineOperatorBuilder::kFloat64RoundDown |
-             MachineOperatorBuilder::kFloat32RoundUp |
-             MachineOperatorBuilder::kFloat64RoundUp |
-             MachineOperatorBuilder::kFloat32RoundTruncate |
-             MachineOperatorBuilder::kFloat64RoundTruncate |
-             MachineOperatorBuilder::kFloat32RoundTiesEven |
-             MachineOperatorBuilder::kFloat64RoundTiesEven;
-  }
   return flags;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8