Subzero. ARM32. Adds header to auto-generated register def file.

pydir/gen_arm32_reg_tables.py

Index: pydir/gen_arm32_reg_tables.py
diff --git a/pydir/gen_arm32_reg_tables.py b/pydir/gen_arm32_reg_tables.py
index cf628712011fd98c7c74f5ac67b0f2ba4cc01b9c..749a119cc3d1884da1fc78ea6192aea90600ee9f 100644
--- a/pydir/gen_arm32_reg_tables.py
+++ b/pydir/gen_arm32_reg_tables.py
@@ -53,6 +53,9 @@ class RegFeatures(object):
     return any(self.FeaturesDict[FpFeature] for FpFeature in (
                    'IsFP32', 'IsFP64', 'IsVec128'))
 
+  def DefiningXMacro(self):
+    return 'define X({parameters})'.format(parameters=', '.join(self.Features))
+
 class Reg(object):
   def __init__(self, Name, Encode, AsmStr=None, **Features):
     self.Name = Name
@@ -68,6 +71,9 @@ class Reg(object):
   def IsAnAliasOf(self, Other):
     return Other.Name in self.Features.Aliases().Aliases
 
+  def DefiningXMacro(self):
+    return self.Features.DefiningXMacro()
+
 # Note: The following tables break the usual 80-col on purpose -- it is easier
 # to read the register tables if each register entry is contained on a single
 # line.
@@ -214,8 +220,9 @@ print ("// This file was auto generated by the {script} script.\n"
        "\n"
        "#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF\n"
        "#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basename(sys.argv[0])))
- 
+
 for Name, RegClass in RegClasses:
+  print '\n//{xmacro}'.format(xmacro=Reg.DefiningXMacro())
   print "#define REGARM32_%s_TABLE" % Name,
   for Reg in RegClass:
     print '\\\n  X({Reg})'.format(Reg=Reg),