Subzero. ARM32. Adds header to auto-generated register def file.

pydir/gen_arm32_reg_tables.py

 import os
 import sys
 
 class RegAliases(object):
   def __init__(self, AliasesStr):
     self.Aliases = list(Alias.strip() for Alias in AliasesStr.split(','))
 
   def __str__(self):
     return 'REGLIST{AliasCount}(RegARM32, {Aliases})'.format(
       AliasCount=len(self.Aliases), Aliases=', '.join(self.Aliases))
@@ skipping 35 matching lines @@
 
   def LivesInGPR(self):
     return (any(self.FeaturesDict[IntFeature] for IntFeature in (
                    'IsInt', 'IsI64Pair', 'IsStackPtr', 'IsFramePtr')) or
             not self.LivesInVFP())
 
   def LivesInVFP(self):
     return any(self.FeaturesDict[FpFeature] for FpFeature in (
                    'IsFP32', 'IsFP64', 'IsVec128'))
 
+  def DefiningXMacro(self):
+    return 'define X({parameters})'.format(parameters=', '.join(self.Features))
+
 class Reg(object):
   def __init__(self, Name, Encode, AsmStr=None, **Features):
     self.Name = Name
     self.Encode = Encode
     if not AsmStr:
       AsmStr = '%s' % Name
     self.Features = RegFeatures(AsmStr=AsmStr, **Features)
 
   def __str__(self):
     return 'Reg_{Name}, {Encode}, {Features}'.format(Name=self.Name,
       Encode=self.Encode, Features=self.Features)
 
   def IsAnAliasOf(self, Other):
     return Other.Name in self.Features.Aliases().Aliases
 
+  def DefiningXMacro(self):
+    return self.Features.DefiningXMacro()
+
 # Note: The following tables break the usual 80-col on purpose -- it is easier
 # to read the register tables if each register entry is contained on a single
 # line.
 GPRs = [
   Reg( 'r0',  0,   IsScratch=1, CCArg=1, IsGPR = 1, IsInt=1,               Aliases= 'r0,  r0r1'),
   Reg( 'r1',  1,   IsScratch=1, CCArg=2, IsGPR = 1, IsInt=1,               Aliases= 'r1,  r0r1'),
   Reg( 'r2',  2,   IsScratch=1, CCArg=3, IsGPR = 1, IsInt=1,               Aliases= 'r2,  r2r3'),
   Reg( 'r3',  3,   IsScratch=1, CCArg=4, IsGPR = 1, IsInt=1,               Aliases= 'r3,  r2r3'),
   Reg( 'r4',  4, IsPreserved=1,          IsGPR = 1, IsInt=1,               Aliases= 'r4,  r4r5'),
   Reg( 'r5',  5, IsPreserved=1,          IsGPR = 1, IsInt=1,               Aliases= 'r5,  r4r5'),
@@ skipping 126 matching lines @@
       assert (AllRegs[Alias].Features.LivesInGPR() ==
                  Reg.Features.LivesInGPR()), '%s VS %s' % (Reg, AllRegs[Alias])
       assert (AllRegs[Alias].Features.LivesInVFP() ==
                  Reg.Features.LivesInVFP()), '%s VS %s' % (Reg, AllRegs[Alias])
 
 print ("// This file was auto generated by the {script} script.\n"
        "// Do not modify it: modify the script instead.\n"
        "\n"
        "#ifndef SUBZERO_SRC_ICEREGISTERSARM32_DEF\n"
        "#define SUBZERO_SRC_ICEREGISTERSARM32_DEF\n".format(script=os.path.basename(sys.argv[0])))
- 
+
 for Name, RegClass in RegClasses:
+  print '\n//{xmacro}'.format(xmacro=Reg.DefiningXMacro())
   print "#define REGARM32_%s_TABLE" % Name,
   for Reg in RegClass:
     print '\\\n  X({Reg})'.format(Reg=Reg),
   print '\n'
 print "#endif // SUBZERO_SRC_ICEREGISTERSARM32_DEF",