| Index: base/cpu.cc
|
| diff --git a/base/cpu.cc b/base/cpu.cc
|
| index ecffb8612448ce9bf9a6b036bdcf936b5f2ddef7..71354456643954ad59238ed23c3b63b9854ab793 100644
|
| --- a/base/cpu.cc
|
| +++ b/base/cpu.cc
|
| @@ -4,12 +4,15 @@
|
|
|
| #include "base/cpu.h"
|
|
|
| +#include <limits.h>
|
| +#include <stddef.h>
|
| +#include <stdint.h>
|
| #include <stdlib.h>
|
| #include <string.h>
|
|
|
| #include <algorithm>
|
|
|
| -#include "base/basictypes.h"
|
| +#include "base/macros.h"
|
| #include "base/strings/string_piece.h"
|
| #include "build/build_config.h"
|
|
|
| @@ -82,12 +85,12 @@ void __cpuid(int cpu_info[4], int info_type) {
|
|
|
| // _xgetbv returns the value of an Intel Extended Control Register (XCR).
|
| // Currently only XCR0 is defined by Intel so |xcr| should always be zero.
|
| -uint64 _xgetbv(uint32 xcr) {
|
| - uint32 eax, edx;
|
| +uint64_t _xgetbv(uint32_t xcr) {
|
| + uint32_t eax, edx;
|
|
|
| __asm__ volatile (
|
| "xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
|
| - return (static_cast<uint64>(edx) << 32) | eax;
|
| + return (static_cast<uint64_t>(edx) << 32) | eax;
|
| }
|
|
|
| #endif // !_MSC_VER
|
|
|