Switch to standard integer types in base/.

base/cpu.cc

 // Copyright (c) 2012 The Chromium Authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "base/cpu.h"
 
+#include <limits.h>
+#include <stddef.h>
+#include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
 
 #include <algorithm>
 
-#include "base/basictypes.h"
+#include "base/macros.h"
 #include "base/strings/string_piece.h"
 #include "build/build_config.h"
 
 #if defined(ARCH_CPU_ARM_FAMILY) && (defined(OS_ANDROID) || defined(OS_LINUX))
 #include "base/files/file_util.h"
 #include "base/lazy_instance.h"
 #endif
 
 #if defined(ARCH_CPU_X86_FAMILY)
 #if defined(_MSC_VER)
@@ skipping 52 matching lines @@
     "cpuid\n"
     : "=a"(cpu_info[0]), "=b"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3])
     : "a"(info_type)
   );
 }
 
 #endif
 
 // _xgetbv returns the value of an Intel Extended Control Register (XCR).
 // Currently only XCR0 is defined by Intel so |xcr| should always be zero.
-uint64 _xgetbv(uint32 xcr) {
-  uint32 eax, edx;
+uint64_t _xgetbv(uint32_t xcr) {
+  uint32_t eax, edx;
 
   __asm__ volatile (
     "xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
-  return (static_cast<uint64>(edx) << 32) | eax;
+  return (static_cast<uint64_t>(edx) << 32) | eax;
 }
 
 #endif  // !_MSC_VER
 #endif  // ARCH_CPU_X86_FAMILY
 
 #if defined(ARCH_CPU_ARM_FAMILY) && (defined(OS_ANDROID) || defined(OS_LINUX))
 class LazyCpuInfoValue {
  public:
   LazyCpuInfoValue() : has_broken_neon_(false) {
     // This function finds the value from /proc/cpuinfo under the key "model
@@ skipping 183 matching lines @@
   if (has_sse42()) return SSE42;
   if (has_sse41()) return SSE41;
   if (has_ssse3()) return SSSE3;
   if (has_sse3()) return SSE3;
   if (has_sse2()) return SSE2;
   if (has_sse()) return SSE;
   return PENTIUM;
 }
 
 }  // namespace base