| Index: src/IceInstARM32.h
|
| diff --git a/src/IceInstARM32.h b/src/IceInstARM32.h
|
| index 75f48a7ff82f70f07d356c834d8c6ed8e20e522b..fd559c293e3020b8746f4e0b895e5f90391337f4 100644
|
| --- a/src/IceInstARM32.h
|
| +++ b/src/IceInstARM32.h
|
| @@ -27,6 +27,12 @@
|
| namespace Ice {
|
| namespace ARM32 {
|
|
|
| +/// Encoding of an ARM 32-bit instruction.
|
| +using IValueT = uint32_t;
|
| +
|
| +/// An Offset value (+/-) used in an ARM 32-bit instruction.
|
| +using IOffsetT = int32_t;
|
| +
|
| class TargetARM32;
|
|
|
| /// OperandARM32 extends the Operand hierarchy. Its subclasses are
|
| @@ -364,6 +370,9 @@ class InstARM32 : public InstTarget {
|
| InstARM32 &operator=(const InstARM32 &) = delete;
|
|
|
| public:
|
| + // Defines form that assembly instruction should be synthesized.
|
| + enum OutputForm { TextualOutput, BinaryOutput };
|
| +
|
| enum InstKindARM32 {
|
| k__Start = Inst::Target,
|
| Adc,
|
| @@ -429,6 +438,8 @@ public:
|
| static const char *getVecWidthString(Type Ty);
|
| static CondARM32::Cond getOppositeCondition(CondARM32::Cond Cond);
|
|
|
| + template <OutputForm> inline void startNextAsmInst(const Cfg *Func) const;
|
| +
|
| /// Called inside derived methods emit() to communicate that multiple
|
| /// instructions are being generated. Used by emitIAS() methods to
|
| /// generate textual fixups for instructions that are not yet
|
| @@ -1073,7 +1084,15 @@ public:
|
|
|
| private:
|
| InstARM32Pop(Cfg *Func, const VarList &Dests);
|
| -
|
| + template <OutputForm> inline void assemble(const Cfg *Func) const;
|
| + void emitPop(const Cfg *Func) const;
|
| + template <OutputForm>
|
| + inline void emitPop(const Cfg *Func, const Variable *Reg) const;
|
| + template <OutputForm>
|
| + inline void emitPopList(const Cfg *Func, ARM32::IValueT Registers) const;
|
| + template <OutputForm>
|
| + inline void emitVpop(const Cfg *Func, const Variable *BaseReg,
|
| + SizeT RegCount) const;
|
| VarList Dests;
|
| };
|
|
|
| @@ -1095,6 +1114,15 @@ public:
|
|
|
| private:
|
| InstARM32Push(Cfg *Func, const VarList &Srcs);
|
| + void emitPush(const Cfg *Func) const;
|
| + template <OutputForm> inline void assemble(const Cfg *Func) const;
|
| + template <OutputForm>
|
| + inline void emitPush(const Cfg *Func, const Variable *Reg) const;
|
| + template <OutputForm>
|
| + inline void emitPushList(const Cfg *Func, ARM32::IValueT Registers) const;
|
| + template <OutputForm>
|
| + inline void emitVPush(const Cfg *Func, const Variable *BaseReg,
|
| + SizeT RegCount) const;
|
| };
|
|
|
| /// Ret pseudo-instruction. This is actually a "bx" instruction with an "lr"
|
|
|