Refactor PUSH/POP in ARM assemblers.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index cb3816fe549c104fdf2b33f27be04f71188538eb..f2d01c06fbd11a46d1592c9085b7cd49a1f61198 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -196,18 +196,6 @@ enum OpEncoding {
   OpEncodingMemEx
 };
 
-IValueT getEncodedGPRegNum(const Variable *Var) {
-  int32_t Reg = Var->getRegNum();
-  return llvm::isa<Variable64On32>(Var) ? RegARM32::getI64PairFirstGPRNum(Reg)
-                                        : RegARM32::getEncodedGPR(Reg);
-}
-
-IValueT getEncodedSRegNum(const Variable *Var) {
-  assert(Var->hasReg());
-  assert(RegARM32::isEncodedSReg(Var->getRegNum()));
-  return RegARM32::getEncodedSReg(Var->getRegNum());
-}
-
 // The way an operand is encoded into a sequence of bits in functions
 // encodeOperand and encodeAddress below.
 enum EncodedOperand {
@@ -282,7 +270,7 @@ EncodedOperand encodeOperand(const Operand *Opnd, IValueT &Value) {
   Value = 0; // Make sure initialized.
   if (const auto *Var = llvm::dyn_cast<Variable>(Opnd)) {
     if (Var->hasReg()) {
-      Value = getEncodedGPRegNum(Var);
+      Value = ARM32::AssemblerARM32::getEncodedGPRegNum(Var);
       return EncodedAsRegister;
     }
     return CantEncode;
@@ -396,14 +384,15 @@ EncodedOperand encodeAddress(const Operand *Opnd, IValueT &Value,
     Variable *Var = Mem->getBase();
     if (!Var->hasReg())
       return CantEncode;
-    IValueT Rn = getEncodedGPRegNum(Var);
+    IValueT Rn = ARM32::AssemblerARM32::getEncodedGPRegNum(Var);
     if (Mem->isRegReg()) {
       const Variable *Index = Mem->getIndex();
       if (Var == nullptr)
         return CantEncode;
       Value = (Rn << kRnShift) | Mem->getAddrMode() |
-              encodeShiftRotateImm5(getEncodedGPRegNum(Index),
-                                    Mem->getShiftOp(), Mem->getShiftAmt());
+              encodeShiftRotateImm5(
+                  ARM32::AssemblerARM32::getEncodedGPRegNum(Index),
+                  Mem->getShiftOp(), Mem->getShiftAmt());
       return EncodedAsShiftRotateImm5;
     }
     // Encoded as immediate register offset.
@@ -535,6 +524,18 @@ void AssemblerARM32::padWithNop(intptr_t Padding) {
     nop();
 }
 
+IValueT AssemblerARM32::getEncodedGPRegNum(const Variable *Var) {
+  int32_t Reg = Var->getRegNum();
+  return llvm::isa<Variable64On32>(Var) ? RegARM32::getI64PairFirstGPRNum(Reg)
+                                        : RegARM32::getEncodedGPR(Reg);
+}
+
+IValueT AssemblerARM32::getEncodedSRegNum(const Variable *Var) {
+  assert(Var->hasReg());

[John, 2016/01/06 16:10:21]

optional: This assertion is not needed -- Var->getRegNum() will assert for you.

[Karl, 2016/01/06 23:21:58]

Done.

+  assert(RegARM32::isEncodedSReg(Var->getRegNum()));
+  return RegARM32::getEncodedSReg(Var->getRegNum());
+}
+
 BlRelocatableFixup *
 AssemblerARM32::createBlFixup(const ConstantRelocatable *BlTarget) {
   BlRelocatableFixup *F =
@@ -1688,13 +1689,13 @@ void AssemblerARM32::orr(const Operand *OpRd, const Operand *OpRn,
              OrrName);
 }
 
-void AssemblerARM32::pop(const Operand *OpRt, CondARM32::Cond Cond) {
+void AssemblerARM32::pop(const Variable *OpRt, CondARM32::Cond Cond) {
   // POP - ARM section A8.8.132, encoding A2:
   //   pop<c> {Rt}
   //
   // cccc010010011101dddd000000000100 where dddd=Rt and cccc=Cond.
   constexpr const char *Pop = "pop";
-  IValueT Rt = encodeRegister(OpRt, "Rt", Pop);
+  const IValueT Rt = encodeRegister(OpRt, "Rt", Pop);
   verifyRegsNotEq(Rt, "Rt", RegARM32::Encoded_Reg_sp, "sp", Pop);
   // Same as load instruction.
   constexpr bool IsLoad = true;
@@ -2009,7 +2010,6 @@ void AssemblerARM32::uxt(const Operand *OpRd, const Operand *OpSrc0,
 void AssemblerARM32::emitVStackOp(CondARM32::Cond Cond, IValueT Opcode,
                                   const Variable *OpBaseReg,
                                   SizeT NumConsecRegs, const char *InstName) {
-
   const IValueT BaseReg = getEncodedSRegNum(OpBaseReg);
   const IValueT DLastBit = mask(BaseReg, 0, 1); // Last bit of base register.
   const IValueT Rd = mask(BaseReg, 1, 4);       // Top 4 bits of base register.