Index: src/IceTargetLoweringX8632.cpp |
diff --git a/src/IceTargetLoweringX8632.cpp b/src/IceTargetLoweringX8632.cpp |
index a09629c477d7f6f4032eeeca09580128c0464a1d..94e7286bed6d8a1f4f92f00e4c8a8b5d5c33233b 100644 |
--- a/src/IceTargetLoweringX8632.cpp |
+++ b/src/IceTargetLoweringX8632.cpp |
@@ -205,7 +205,11 @@ void TargetX8632::lowerCall(const InstCall *Instr) { |
break; |
case IceType_i1: |
case IceType_i8: |
+ ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_al); |
+ break; |
case IceType_i16: |
+ ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_ax); |
+ break; |
case IceType_i32: |
ReturnReg = makeReg(Dest->getType(), Traits::RegisterSet::Reg_eax); |
Jim Stichnoth
2015/12/20 18:42:23
Instead of the above, I think you could do somethi
sehr
2016/01/07 18:53:11
Done.
|
break; |
@@ -342,6 +346,11 @@ void TargetX8632::lowerRet(const InstRet *Inst) { |
_fld(Src0); |
} else if (isVectorType(Src0->getType())) { |
Reg = legalizeToReg(Src0, Traits::RegisterSet::Reg_xmm0); |
+ } else if (Src0->getType() == IceType_i8) { |
Jim Stichnoth
2015/12/20 18:42:23
Maybe check against i1 as well, for completeness
sehr
2016/01/07 18:53:11
I converted these all to use the getGprForType sch
|
+ // TODO(sehr,stichnot): I think these need to sign/zero extend. |
Jim Stichnoth
2015/12/20 18:42:23
I don't think the x86-32 processor ABI has anythin
sehr
2016/01/07 18:53:11
I'm going with the idea that we're doing this for
|
+ _mov(Reg, Src0, Traits::RegisterSet::Reg_al); |
+ } else if (Src0->getType() == IceType_i16) { |
+ _mov(Reg, Src0, Traits::RegisterSet::Reg_ax); |
} else { |
_mov(Reg, Src0, Traits::RegisterSet::Reg_eax); |
} |