Add trap (an UDF instruction) to the ARM integrated Assembler.

src/IceAssemblerARM32.cpp

Index: src/IceAssemblerARM32.cpp
diff --git a/src/IceAssemblerARM32.cpp b/src/IceAssemblerARM32.cpp
index 0d5dc380efc64a554729e9ad491b814f2538e76e..bf156f5c624c67ba8076ef3749a5cb02dcca6774 100644
--- a/src/IceAssemblerARM32.cpp
+++ b/src/IceAssemblerARM32.cpp
@@ -1873,6 +1873,21 @@ void AssemblerARM32::sub(const Operand *OpRd, const Operand *OpRn,
              SubName);
 }
 
+// Use a particular UDF encoding -- TRAPNaCl in LLVM: 0xE7FEDEF0
+// http://llvm.org/viewvc/llvm-project?view=revision&revision=173943
+const uint8_t AssemblerARM32::TrapInst[] = {0xE7, 0xFE, 0xDE, 0xF0};
+
+llvm::ArrayRef<uint8_t> AssemblerARM32::getNonExecBundlePadding() const {
+  return llvm::ArrayRef<uint8_t>(TrapInst, llvm::array_lengthof(TrapInst));
+}
+
+void AssemblerARM32::trap() {
+  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
+  for (size_t i = llvm::array_lengthof(TrapInst); i > 0; --i) {

[Jim Stichnoth, 2015/12/17 16:41:00]

Actually, one more (optional) idea that adds a lot more clarity, I think (though
at the cost of minor efficiency):

  auto Bytes = getNonExecBundlePadding();
  for (const uint8_t &Byte : reverse_range(Bytes)) {
    Buffer.emit<uint8_t>(Byte);
  }

To address the efficiency issue, here's another version that could probably use
a bit more cleanup:

namespace {
const uint8_t TrapBytesRaw[] = {0xE7, 0xFE, 0xDE, 0xF0};
const auto TrapBytes =
  llvm::ArrayRef<uint8_t>(TrapBytesRaw, llvm::array_lengthof(TrapBytesRaw));
} // end of anonymous namespace

llvm::ArrayRef<uint8_t> AssemblerARM32::getNonExecBundlePadding() const {
  return TrapBytes;
}

void AssemblerARM32::trap() {
  AssemblerBuffer::EnsureCapacity ensured(&Buffer);
  for (const uint8_t &Byte : reverse_range(TrapBytes)) {
    Buffer.emit<uint8_t>(Byte);
  }
}

[Karl, 2015/12/17 16:55:28]

Done.

+    Buffer.emit<uint8_t>(TrapInst[i - 1]);
+  }
+}
+
 void AssemblerARM32::tst(const Operand *OpRn, const Operand *OpSrc1,
                          CondARM32::Cond Cond) {
   // TST (register) - ARM section A8.8.241, encoding A1: