MIPS: [turbofan] Fixed Div operations by zero on r6.

src/compiler/mips/code-generator-mips.cc

Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc
index 3eaaed8081594a522cfa57e7907f81a0e90f4d46..aee85d9583ee336e234b5316bff2fa0b7e1dd235 100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -648,7 +648,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
     case kMipsDiv:
       __ Div(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
       if (IsMipsArchVariant(kMips32r6)) {
-        __ selnez(i.OutputRegister(), i.InputRegister(1), i.InputRegister(0));
+        __ selnez(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1));
       }
@@ -656,7 +656,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
     case kMipsDivU:
       __ Divu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
       if (IsMipsArchVariant(kMips32r6)) {
-        __ selnez(i.OutputRegister(), i.InputRegister(1), i.InputRegister(0));
+        __ selnez(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1));
       } else {
         __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1));
       }