MIPS: [turbofan] Fix Div operations by zero on r6.

src/compiler/mips/code-generator-mips.cc

Index: src/compiler/mips/code-generator-mips.cc
diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc
index 70fd567693644775a7735e519365bd6f33c94f79..849d80f4673b234fb986b8a6a9c63b671ae2a46f 100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -636,7 +636,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
     case kMipsDiv:
       __ Div(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
       if (IsMipsArchVariant(kMips32r6)) {
-        __ seleqz(i.OutputRegister(), i.InputRegister(0), i.InputRegister(0));
+        __ selnez(i.OutputRegister(), i.InputRegister(1), i.InputRegister(0));
       } else {
         __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1));
       }
@@ -644,7 +644,7 @@ void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
     case kMipsDivU:
       __ Divu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
       if (IsMipsArchVariant(kMips32r6)) {
-        __ seleqz(i.OutputRegister(), i.InputRegister(0), i.InputRegister(0));
+        __ selnez(i.OutputRegister(), i.InputRegister(1), i.InputRegister(0));
       } else {
         __ Movz(i.OutputRegister(), i.InputRegister(1), i.InputRegister(1));
       }