Subzero: Add Non-SFI support for x86-32.

src/IceTargetLoweringX8664Traits.h

Index: src/IceTargetLoweringX8664Traits.h
diff --git a/src/IceTargetLoweringX8664Traits.h b/src/IceTargetLoweringX8664Traits.h
index 6e26945d23139f921bb72153fdcaa43fc5e6292d..8fa088234abe2ac1015b6ff511c095b65d4c0fd0 100644
--- a/src/IceTargetLoweringX8664Traits.h
+++ b/src/IceTargetLoweringX8664Traits.h
@@ -69,8 +69,10 @@ template <> struct MachineTraits<TargetX8664> {
   using RegisterSet = ::Ice::RegX8664;
   static const GPRRegister Encoded_Reg_Accumulator = RegX8664::Encoded_Reg_eax;
   static const GPRRegister Encoded_Reg_Counter = RegX8664::Encoded_Reg_ecx;
-  static const FixupKind PcRelFixup = llvm::ELF::R_X86_64_PC32;
-  static const FixupKind RelFixup = llvm::ELF::R_X86_64_32S;
+  static constexpr FixupKind FixupKindPcRel = llvm::ELF::R_X86_64_PC32;
+  static constexpr FixupKind FixupKindAbs = llvm::ELF::R_X86_64_32S;
+  static constexpr FixupKind FixupKindGotoff = llvm::ELF::R_X86_64_GOTOFF64;
+  static constexpr FixupKind FixupKindGotPC = llvm::ELF::R_X86_64_GOTPC32;
 
   class Operand {
   public:
@@ -265,7 +267,7 @@ template <> struct MachineTraits<TargetX8664> {
 
     static Address ofConstPool(Assembler *Asm, const Constant *Imm) {
       // TODO(jpp): ???
-      AssemblerFixup *Fixup = Asm->createFixup(RelFixup, Imm);
+      AssemblerFixup *Fixup = Asm->createFixup(FixupKindAbs, Imm);
       const RelocOffsetT Offset = 4;
       return Address(Offset, Fixup);
     }
@@ -705,11 +707,12 @@ template <> struct MachineTraits<TargetX8664> {
     static X86OperandMem *
     create(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
            Variable *Index = nullptr, uint16_t Shift = 0,
-           SegmentRegisters SegmentRegister = DefaultSegment) {
+           SegmentRegisters SegmentRegister = DefaultSegment,
+           bool IsPIC = false) {
       assert(SegmentRegister == DefaultSegment);
       (void)SegmentRegister;
       return new (Func->allocate<X86OperandMem>())
-          X86OperandMem(Func, Ty, Base, Offset, Index, Shift);
+          X86OperandMem(Func, Ty, Base, Offset, Index, Shift, IsPIC);
     }
     Variable *getBase() const { return Base; }
     Constant *getOffset() const { return Offset; }
@@ -717,6 +720,8 @@ template <> struct MachineTraits<TargetX8664> {
     uint16_t getShift() const { return Shift; }
     SegmentRegisters getSegmentRegister() const { return DefaultSegment; }
     void emitSegmentOverride(Assembler *) const {}
+    void setIsPIC() { IsPIC = true; }
+    bool getIsPIC() const { return IsPIC; }
     Address toAsmAddress(Assembler *Asm,
                          const Ice::TargetLowering *Target) const;
 
@@ -734,12 +739,13 @@ template <> struct MachineTraits<TargetX8664> {
 
   private:
     X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
-                  Variable *Index, uint16_t Shift);
+                  Variable *Index, uint16_t Shift, bool IsPIC);
 
     Variable *Base;
     Constant *Offset;
     Variable *Index;
     uint16_t Shift;
+    bool IsPIC;
     /// A flag to show if this memory operand is a randomized one. Randomized
     /// memory operands are generated in
     /// TargetX86Base::randomizeOrPoolImmediate()