Subzero: Add Non-SFI support for x86-32.

src/IceTargetLoweringX8632Traits.h

Index: src/IceTargetLoweringX8632Traits.h
diff --git a/src/IceTargetLoweringX8632Traits.h b/src/IceTargetLoweringX8632Traits.h
index b0738811f32281ab40f93076833a5bb8133202f7..de0c1e703b51b0c41ecb923a7cb43e3f6942234e 100644
--- a/src/IceTargetLoweringX8632Traits.h
+++ b/src/IceTargetLoweringX8632Traits.h
@@ -70,8 +70,10 @@ template <> struct MachineTraits<TargetX8632> {
   using RegisterSet = ::Ice::RegX8632;
   static const GPRRegister Encoded_Reg_Accumulator = RegX8632::Encoded_Reg_eax;
   static const GPRRegister Encoded_Reg_Counter = RegX8632::Encoded_Reg_ecx;
-  static const FixupKind PcRelFixup = llvm::ELF::R_386_PC32;
-  static const FixupKind RelFixup = llvm::ELF::R_386_32;
+  static constexpr FixupKind FixupKindPcRel = llvm::ELF::R_386_PC32;
+  static constexpr FixupKind FixupKindAbs = llvm::ELF::R_386_32;
+  static constexpr FixupKind FixupKindGotoff = llvm::ELF::R_386_GOTOFF;
+  static constexpr FixupKind FixupKindGotPC = llvm::ELF::R_386_GOTPC;
 
   class Operand {
   public:
@@ -727,9 +729,10 @@ template <> struct MachineTraits<TargetX8632> {
     static X86OperandMem *create(Cfg *Func, Type Ty, Variable *Base,
                                  Constant *Offset, Variable *Index = nullptr,
                                  uint16_t Shift = 0,
-                                 SegmentRegisters SegmentReg = DefaultSegment) {
-      return new (Func->allocate<X86OperandMem>())
-          X86OperandMem(Func, Ty, Base, Offset, Index, Shift, SegmentReg);
+                                 SegmentRegisters SegmentReg = DefaultSegment,
+                                 bool IsPIC = false) {
+      return new (Func->allocate<X86OperandMem>()) X86OperandMem(
+          Func, Ty, Base, Offset, Index, Shift, SegmentReg, IsPIC);
     }
     Variable *getBase() const { return Base; }
     Constant *getOffset() const { return Offset; }
@@ -737,6 +740,8 @@ template <> struct MachineTraits<TargetX8632> {
     uint16_t getShift() const { return Shift; }
     SegmentRegisters getSegmentRegister() const { return SegmentReg; }
     void emitSegmentOverride(Assembler *Asm) const;
+    void setIsPIC() { IsPIC = true; }
+    bool getIsPIC() const { return IsPIC; }
     Address toAsmAddress(Assembler *Asm,
                          const Ice::TargetLowering *Target) const;
 
@@ -754,17 +759,19 @@ template <> struct MachineTraits<TargetX8632> {
 
   private:
     X86OperandMem(Cfg *Func, Type Ty, Variable *Base, Constant *Offset,
-                  Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg);
+                  Variable *Index, uint16_t Shift, SegmentRegisters SegmentReg,
+                  bool IsPIC);
 
     Variable *Base;
     Constant *Offset;
     Variable *Index;
     uint16_t Shift;
     SegmentRegisters SegmentReg : 16;
+    bool IsPIC;
     /// A flag to show if this memory operand is a randomized one. Randomized
     /// memory operands are generated in
     /// TargetX86Base::randomizeOrPoolImmediate()
-    bool Randomized;
+    bool Randomized = false;
   };
 
   /// VariableSplit is a way to treat an f64 memory location as a pair of i32