Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(15)

Unified Diff: src/IceTargetLoweringMIPS32.cpp

Issue 1506653002: Subzero: Add Non-SFI support for x86-32. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fill in part of the lit test Created 5 years ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
Index: src/IceTargetLoweringMIPS32.cpp
diff --git a/src/IceTargetLoweringMIPS32.cpp b/src/IceTargetLoweringMIPS32.cpp
index 391a4e94704869f0b80175024607f2247ec674d9..162ebec89ce17482cc6a87fa45c0f374e24f606c 100644
--- a/src/IceTargetLoweringMIPS32.cpp
+++ b/src/IceTargetLoweringMIPS32.cpp
@@ -43,7 +43,8 @@ constexpr uint32_t MIPS32_MAX_GPR_ARG = 4;
TargetMIPS32::TargetMIPS32(Cfg *Func) : TargetLowering(Func) {}
-void TargetMIPS32::staticInit() {
+void TargetMIPS32::staticInit(const ClFlags &Flags) {
+ (void)Flags;
llvm::SmallBitVector IntegerRegisters(RegMIPS32::Reg_NUM);
llvm::SmallBitVector I64PairRegisters(RegMIPS32::Reg_NUM);
llvm::SmallBitVector Float32Registers(RegMIPS32::Reg_NUM);
@@ -961,10 +962,12 @@ TargetDataMIPS32::TargetDataMIPS32(GlobalContext *Ctx)
void TargetDataMIPS32::lowerGlobals(const VariableDeclarationList &Vars,
const IceString &SectionSuffix) {
+ const bool IsPIC = Ctx->getFlags().getUseNonsfi();
switch (Ctx->getFlags().getOutFileType()) {
case FT_Elf: {
ELFObjectWriter *Writer = Ctx->getObjectWriter();
- Writer->writeDataSection(Vars, llvm::ELF::R_MIPS_GLOB_DAT, SectionSuffix);
+ Writer->writeDataSection(Vars, llvm::ELF::R_MIPS_GLOB_DAT, SectionSuffix,
+ IsPIC);
} break;
case FT_Asm:
case FT_Iasm: {

Powered by Google App Engine
This is Rietveld 408576698