Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(26)

Unified Diff: tests_lit/assembler/arm32/lsr.ll

Issue 1501073002: Implement LSR instructions for the integrated ARM assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Fix nit. Created 5 years ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View side-by-side diff with in-line comments
Download patch
« no previous file with comments | « src/IceInstARM32.cpp ('k') | no next file » | no next file with comments »
Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
Index: tests_lit/assembler/arm32/lsr.ll
diff --git a/tests_lit/assembler/arm32/lsl.ll b/tests_lit/assembler/arm32/lsr.ll
similarity index 57%
copy from tests_lit/assembler/arm32/lsl.ll
copy to tests_lit/assembler/arm32/lsr.ll
index e4794bcef472aa63343651c5f3ceedb0c654aee2..f1d1e8a8bab41f3995f47aacf0df9c71ff961edb 100644
--- a/tests_lit/assembler/arm32/lsl.ll
+++ b/tests_lit/assembler/arm32/lsr.ll
@@ -1,4 +1,4 @@
-; Show that we know how to translate lsl.
+; Show that we know how to translate lsr.
; NOTE: We use -O2 to get rid of memory stores.
@@ -20,44 +20,44 @@
; RUN: %p2i --filetype=iasm -i %s --target=arm32 --assemble --disassemble \
; RUN: --args -O2 | FileCheck %s --check-prefix=DIS
-define internal i32 @ShlAmt(i32 %a) {
-; ASM-LABEL:ShlAmt:
-; DIS-LABEL:00000000 <ShlAmt>:
-; IASM-LABEL:ShlAmt:
+define internal i32 @LshrAmt(i32 %a) {
+; ASM-LABEL:LshrAmt:
+; DIS-LABEL:00000000 <LshrAmt>:
+; IASM-LABEL:LshrAmt:
entry:
-; ASM-NEXT:.LShlAmt$entry:
-; IASM-NEXT:.LShlAmt$entry:
+; ASM-NEXT:.LLshrAmt$entry:
+; IASM-NEXT:.LLshrAmt$entry:
- %shl = shl i32 %a, 23
+ %v = lshr i32 %a, 23
-; ASM-NEXT: lsl r0, r0, #23
-; DIS-NEXT: 0: e1a00b80
-; IASM-NEXT: .byte 0x80
+; ASM-NEXT: lsr r0, r0, #23
+; DIS-NEXT: 0: e1a00ba0
+; IASM-NEXT: .byte 0xa0
; IASM-NEXT: .byte 0xb
; IASM-NEXT: .byte 0xa0
; IASM-NEXT: .byte 0xe1
- ret i32 %shl
+ ret i32 %v
}
-define internal i32 @ShlReg(i32 %a, i32 %b) {
-; ASM-LABEL:ShlReg:
-; DIS-LABEL:00000010 <ShlReg>:
-; IASM-LABEL:ShlReg:
+define internal i32 @LshrReg(i32 %a, i32 %b) {
+; ASM-LABEL:LshrReg:
+; DIS-LABEL:00000010 <LshrReg>:
+; IASM-LABEL:LshrReg:
entry:
-; ASM-NEXT:.LShlReg$entry:
-; IASM-NEXT:.LShlReg$entry:
+; ASM-NEXT:.LLshrReg$entry:
+; IASM-NEXT:.LLshrReg$entry:
- %shl = shl i32 %a, %b
+ %v = lshr i32 %a, %b
-; ASM-NEXT: lsl r0, r0, r1
-; DIS-NEXT: 10: e1a00110
-; IASM-NEXT: .byte 0x10
+; ASM-NEXT: lsr r0, r0, r1
+; DIS-NEXT: 10: e1a00130
+; IASM-NEXT: .byte 0x30
; IASM-NEXT: .byte 0x1
; IASM-NEXT: .byte 0xa0
; IASM-NEXT: .byte 0xe1
- ret i32 %shl
+ ret i32 %v
}
« no previous file with comments | « src/IceInstARM32.cpp ('k') | no next file » | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698